[llvm] Use getSignedTargetConstant for offset (PR #141149)
Shimin Cui via llvm-commits
llvm-commits at lists.llvm.org
Thu May 22 15:15:36 PDT 2025
https://github.com/scui-ibm created https://github.com/llvm/llvm-project/pull/141149
This is to fix an assertion failure with PeepholePPC64. The load/store offset can be negative. A reduced case from one of our failures is added as well.
>From ca6d08b908ad17435d1287377ba6905b3ab6ab66 Mon Sep 17 00:00:00 2001
From: Shimin Cui <scui at ca.ibm.com>
Date: Thu, 22 May 2025 18:06:23 -0400
Subject: [PATCH] Use getSignedTargetConstant for offset
---
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 +--
llvm/test/CodeGen/PowerPC/signed-offset.ll | 33 +++++++++++++++++++++
2 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/signed-offset.ll
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 7147506bbd89b..f921032356d65 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -7858,8 +7858,8 @@ void PPCDAGToDAGISel::PeepholePPC64() {
if (!isInt<16>(Offset))
continue;
- ImmOpnd = CurDAG->getTargetConstant(Offset, SDLoc(ImmOpnd),
- ImmOpnd.getValueType());
+ ImmOpnd = CurDAG->getSignedTargetConstant(Offset, SDLoc(ImmOpnd),
+ ImmOpnd.getValueType());
} else if (Offset != 0) {
// This optimization is performed for non-TOC-based local-[exec|dynamic]
// accesses.
diff --git a/llvm/test/CodeGen/PowerPC/signed-offset.ll b/llvm/test/CodeGen/PowerPC/signed-offset.ll
new file mode 100644
index 0000000000000..d12f99ead644b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/signed-offset.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff | FileCheck %s
+
+%_type = type <{ [90112 x i8] }>
+
+ at g = external global %_type
+
+define void @foo(ptr %p) {
+; CHECK-LABEL: foo:
+; CHECK: stfd 31, 0(31)
+; CHECK-NEXT: lwz 3, -32(30)
+; CHECK-NEXT: lwz 4, -28(30)
+; CHECK-NEXT: cmplwi 3, 0
+; CHECK-NEXT: cmpwi 1, 3, 0
+; CHECK-NEXT: crandc 20, 5, 2
+; CHECK-NEXT: cmpwi 1, 4, 0
+entry:
+ %0 = load double, ptr getelementptr inbounds nuw (i8, ptr @g, i32 83272), align 8
+ %1 = call i32 @bar(ptr getelementptr inbounds nuw (i8, ptr @g, i32 83272))
+ %2 = call i32 @bar(ptr getelementptr inbounds nuw (i8, ptr @g, i32 83240))
+ store double %0, ptr %p, align 8
+ %3 = load i64, ptr getelementptr inbounds nuw (i8, ptr @g, i32 83240), align 8
+ %4 = icmp slt i64 %3, 1
+ br i1 %4, label %then, label %else
+
+then: ; preds = %entry
+ ret void
+
+else: ; preds = %entry
+ ret void
+}
+
+declare signext i32 @bar(ptr)
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