[llvm] [NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (PR #141101)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 22 13:39:00 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-hexagon
Author: Rahul Joshi (jurahul)
<details>
<summary>Changes</summary>
---
Patch is 79.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/141101.diff
115 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+6)
- (modified) llvm/include/llvm/CodeGen/PeepholeOptimizer.h (+1-2)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+2-14)
- (modified) llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64CollectLOH.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp (+1-3)
- (modified) llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp (+2-5)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp (+2-5)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp (+2-5)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp (+2-4)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp (+2-4)
- (modified) llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/GCNDPPCombine.h (+1-2)
- (modified) llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIFoldOperands.h (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp (+1-3)
- (modified) llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h (+1-3)
- (modified) llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp (+2-4)
- (modified) llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h (+2-4)
- (modified) llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp (+3-7)
- (modified) llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIWholeQuadMode.h (+1-2)
- (modified) llvm/lib/Target/ARM/ARMConstantIslandPass.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp (+2-4)
- (modified) llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/MVEVPTBlockPass.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/Thumb1FrameLowering.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/Thumb2SizeReduction.cpp (+1-2)
- (modified) llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonGenMux.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp (+1-2)
- (modified) llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (+2-4)
- (modified) llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp (+1-2)
- (modified) llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp (+1-2)
- (modified) llvm/lib/Target/M68k/M68kExpandPseudo.cpp (+1-2)
- (modified) llvm/lib/Target/MSP430/MSP430BranchSelector.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsBranchExpansion.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsConstantIslandPass.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsExpandPseudo.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsMulMulBugPass.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/PowerPC/PPCBranchSelector.cpp (+1-2)
- (modified) llvm/lib/Target/PowerPC/PPCCTRLoops.cpp (+1-2)
- (modified) llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp (+1-2)
- (modified) llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp (+2-5)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+1-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+1-1)
- (modified) llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp (+1-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp (+1-2)
- (modified) llvm/lib/Target/Sparc/DelaySlotFiller.cpp (+1-2)
- (modified) llvm/lib/Target/SystemZ/SystemZElimCompare.cpp (+1-2)
- (modified) llvm/lib/Target/SystemZ/SystemZISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/SystemZ/SystemZLongBranch.cpp (+1-2)
- (modified) llvm/lib/Target/SystemZ/SystemZShortenInst.cpp (+1-2)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86CmovConversion.cpp (+1-1)
- (modified) llvm/lib/Target/X86/X86CompressEVEX.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86ExpandPseudo.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FastTileConfig.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FixupBWInsts.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FixupInstTuning.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FixupLEAs.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FixupVectorConstants.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86FloatingPoint.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86PadShortFunction.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86TileConfig.cpp (+1-2)
- (modified) llvm/lib/Target/X86/X86VZeroUpper.cpp (+1-2)
- (modified) llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp (+1-2)
- (modified) llvm/tools/llvm-exegesis/lib/Assembler.cpp (+2-4)
- (modified) llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp (+1-2)
- (modified) llvm/unittests/MI/LiveIntervalTest.cpp (+1-1)
- (modified) llvm/unittests/MIR/MachineMetadata.cpp (+2-4)
- (modified) llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 81428c6450529..e2379be775cca 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -239,6 +239,12 @@ class MachineFunctionProperties {
return *this;
}
+ // Set all the properties.
+ MachineFunctionProperties &set() {
+ Properties.set();
+ return *this;
+ }
+
MachineFunctionProperties &set(const MachineFunctionProperties &MFP) {
Properties |= MFP.Properties;
return *this;
diff --git a/llvm/include/llvm/CodeGen/PeepholeOptimizer.h b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
index f3968ebb59bce..7f57e6dc35779 100644
--- a/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
+++ b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h
@@ -19,8 +19,7 @@ class PeepholeOptimizerPass : public PassInfoMixin<PeepholeOptimizerPass> {
MachineFunctionAnalysisManager &MFAM);
MachineFunctionProperties getRequiredProperties() const {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
+ return MachineFunctionProperties().setIsSSA();
}
};
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 56e91703cb019..086ddc8ff7731 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -447,7 +447,7 @@ class TriggerVerifierErrorPass
// Intentionally create a virtual register and set NoVRegs property.
auto &MRI = MF.getRegInfo();
MRI.createGenericVirtualRegister(LLT::scalar(8));
- MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+ MF.getProperties().setNoVRegs();
return PreservedAnalyses::all();
}
@@ -465,19 +465,7 @@ class RequireAllMachineFunctionPropertiesPass
}
static MachineFunctionProperties getRequiredProperties() {
- MachineFunctionProperties MFProps;
- MFProps.set(MachineFunctionProperties::Property::FailedISel);
- MFProps.set(MachineFunctionProperties::Property::FailsVerification);
- MFProps.set(MachineFunctionProperties::Property::IsSSA);
- MFProps.set(MachineFunctionProperties::Property::Legalized);
- MFProps.set(MachineFunctionProperties::Property::NoPHIs);
- MFProps.set(MachineFunctionProperties::Property::NoVRegs);
- MFProps.set(MachineFunctionProperties::Property::RegBankSelected);
- MFProps.set(MachineFunctionProperties::Property::Selected);
- MFProps.set(MachineFunctionProperties::Property::TiedOpsRewritten);
- MFProps.set(MachineFunctionProperties::Property::TracksDebugUserValues);
- MFProps.set(MachineFunctionProperties::Property::TracksLiveness);
- return MFProps;
+ return MachineFunctionProperties().set();
}
static StringRef name() { return "RequireAllMachineFunctionPropertiesPass"; }
};
diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
index 2760355ae6107..a51f63073403b 100644
--- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp
@@ -86,8 +86,7 @@ class AArch64A53Fix835769 : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override {
diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
index 87bc925c6dc16..b816f11508bed 100644
--- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
+++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
@@ -117,8 +117,7 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override {
diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
index c3370cd6e946c..64f21c4cb2297 100644
--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -132,8 +132,7 @@ struct AArch64CollectLOH : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }
diff --git a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
index 6621a1f2fc764..37ad308e4287d 100644
--- a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp
@@ -52,8 +52,7 @@ class AArch64CompressJumpTables : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override {
return "AArch64 Compress Jump Tables";
diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
index 9a88240de1811..83804b4b09bc4 100644
--- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
@@ -188,8 +188,7 @@ class FalkorHWPFFix : public MachineFunctionPass {
}
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
private:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 22ecf99b12de6..61055a66e8858 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1121,7 +1121,7 @@ let RecomputePerFunction = 1 in {
// SelectionDAG's behaviour.
// FIXME: One day there will probably be a nicer way to check for this, but
// today is not that day.
- def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">;
+ def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">;
}
include "AArch64InstrFormats.td"
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index dc866486fb953..b7da07a95c7b4 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -233,8 +233,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }
diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
index 7cdcd5416cfc1..66f14b67a31ff 100644
--- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
@@ -173,9 +173,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M,
MachineFunction &MF = MMI->getOrCreateMachineFunction(*F);
// Remove unnecessary register liveness and set NoVRegs.
- MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness);
- MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
- MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+ MF.getProperties().resetTracksLiveness().resetIsSSA().setNoVRegs();
MF.getRegInfo().freezeReservedRegs();
// Create entry block.
diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
index 9c1ab06e1c1c0..84015e5061768 100644
--- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -92,8 +92,7 @@ class AArch64RedundantCopyElimination : public MachineFunctionPass {
bool optimizeBlock(MachineBasicBlock *MBB);
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ return MachineFunctionProperties().setNoVRegs();
}
StringRef getPassName() const override {
return "AArch64 Redundant Copy Elimination";
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 1dc7318f58990..8caa49de0af43 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -544,8 +544,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// the pipeline since it prevents other infrastructure from reasoning about
// it's liveness. We use the NoVRegs property instead of IsSSA because
// IsSSA is removed before VirtRegRewriter runs.
- if (!MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::NoVRegs))
+ if (!MF.getProperties().hasNoVRegs())
markSuperRegs(Reserved, AArch64::LR);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
index cca0adc84f6f6..b5047a88fbaf6 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
@@ -147,8 +147,7 @@ AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner()
}
bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
auto &TPC = getAnalysis<TargetPassConfig>();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 1c3d2b4166309..fa7bb6ecc35ee 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -654,12 +654,9 @@ AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
}
bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
- assert(MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::Legalized) &&
- "Expected a legalized function?");
+ assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
bool EnableOpt =
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 81ee525ed0501..1f547de8c0523 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -1257,12 +1257,9 @@ AArch64PostLegalizerLowering::AArch64PostLegalizerLowering()
}
bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
- assert(MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::Legalized) &&
- "Expected a legalized function?");
+ assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
index 913a8870565d9..4bd025da636ca 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
@@ -292,12 +292,9 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
}
bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
- assert(MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::Selected) &&
- "Expected a selected MF");
+ assert(MF.getProperties().hasSelected() && "Expected a selected MF");
bool Changed = false;
for (auto &BB : MF) {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index 37a7d2206b180..1cd94531c3620 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -836,8 +836,7 @@ AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
}
bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
auto &TPC = getAnalysis<TargetPassConfig>();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
index 0c6122cce78e0..e86b4738bed18 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
@@ -478,8 +478,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
}
bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
index 4aec2ba35ae5d..6e54737065d20 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
@@ -253,8 +253,7 @@ AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
}
bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index f08502fb3d928..ee324a5e93f0f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -462,8 +462,7 @@ AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
}
bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
const Function &F = MF.getFunction();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
index ad6a0772fe8b6..4d8d3022b8080 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp
@@ -58,8 +58,7 @@ class AMDGPURegBankLegalize : public MachineFunctionPass {
// If there were no phis and we do waterfall expansion machine verifier would
// fail.
MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoPHIs);
+ return MachineFunctionProperties().setNoPHIs();
}
};
@@ -250,8 +249,7 @@ class AMDGPURegBankLegalizeCombiner {
}
bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
// Setup the instruction builder with CSE.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
index fe73aac0763e0..493b7541cdd81 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
@@ -53,8 +53,7 @@ class AMDGPURegBankSelect : public MachineFunctionPass {
// This pass assigns register banks to all virtual registers, and we maintain
// this property in subsequent passes
MachineFunctionProperties getSetProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::RegBankSelected);
+ return MachineFunctionProperties().setRegBankSelected();
}
};
@@ -199,8 +198,7 @@ static Register getVReg(MachineOperand &Op) {
}
bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
- if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedISel))
+ if (MF.getProperties().hasFailedISel())
return false;
// Setup the instruction builder with CSE.
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index 0d8113da275bd..f9a907a644373 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -98,8 +98,7 @@ class GCNDPPCombineLegacy : public MachineFunctionPass {
}
MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties()
- .set(MachineFunctionProperties::Property::IsSSA);
+ return MachineFunctionProperties().setIsSSA();
}
};
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.h b/llvm/lib/Target/AMDGPU/GCNDPPCombine.h
index ac45e578157ee..cc8979b858b93 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.h
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.h
@@ -18,8 +18,7 @@ class GCNDPPCombinePass : public PassInfoMixin<GCNDPPCombinePass> {
MachineFunctionAnalysisManager &MAM);
MachineFunctionProperties getRequiredProperties() const {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
+ return MachineFunctionProperties().setIsSSA();
}
};
diff --git a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
index b3dd68b6a1433..d9902e121f9c2 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp
@@ -121,8 +121,7 @@ class R600MachineCFGStructurizer : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override {
// FIXME: This pass ca...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/141101
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