[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Matt Arsenault via llvm-commits]

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@@ -5929,6 +5944,36 @@ SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
   return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
 }
 
+// Enable lowering of ROTR for vxi32 types.
+SDValue SITargetLowering::lowerROTR(SDValue Op, SelectionDAG &DAG) const {
+  unsigned Opc = Op.getOpcode();
+  EVT VT = Op.getValueType();
+  assert(Opc == ISD::ROTR && "Expected ROTR Opcode for lowerROTR.");
+
+  assert((VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v8i32 ||
+          VT == MVT::v16i32) &&
+         "Unexpected ValueType.");
+
+  unsigned VectorSize = VT.getVectorNumElements();
+  EVT ElementType = VT.getVectorElementType();
+  SDLoc SL(Op);
+  auto LHS = Op->getOperand(0);
+  auto RHS = Op->getOperand(1);
+
+  SmallVector<SDValue, 4> RotateTargets;
+  SmallVector<SDValue, 4> RotateSizes;
+  SmallVector<SDValue, 4> Ops;
+
+  DAG.ExtractVectorElements(LHS, RotateTargets, 0, VectorSize, ElementType);
+  DAG.ExtractVectorElements(RHS, RotateSizes, 0, VectorSize, ElementType);
+
+  for (unsigned i = 0; i < VectorSize; i++)
+    Ops.push_back(DAG.getNode(ISD::ROTR, SL, ElementType, RotateTargets[i],
+                              RotateSizes[i], Op->getFlags()));
+
+  return DAG.getBuildVector(VT, SL, Ops);
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arsenm wrote:

Can use DAG.UnrollVectorOp 

https://github.com/llvm/llvm-project/pull/140694