[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[Chris Jackson via llvm-commits]

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@@ -0,0 +1,32 @@
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs  -debug-only=isel  %s -o - 2>&1 | FileCheck -check-prefixes=DEBUG,SI %s
+; REQUIRES: asserts
+
+; DEBUG-LABEL: Optimized legalized selection DAG: %bb.0 'rotr_v2i32:entry'
+; DEBUG: t[[V1:[0-9]+]]: v2i32 = BUILD_VECTOR t{{[0-9]+}}, t{{[0-9]+}}
+; DEBUG: t[[V2:[0-9]+]]: v2i32 = BUILD_VECTOR t{{[0-9]+}}, t{{[0-9]+}}
+; DEBUG: t{{[0-9]+}}: v2i32 = rotr t[[V1]], t[[V2]]
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chrisjbris wrote:

This test no longer has any value as the implementation has been moved to the legalizer and is generalised for all vector widths (though I currently assert if the vector is not of specific widths as I'm not sure which should be legal).

https://github.com/llvm/llvm-project/pull/140694