[llvm] [AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (PR #140062)

[Paul Walker via llvm-commits]

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@@ -310,22 +151,45 @@ define <vscale x 32 x i1> @lane_mask_nxv32i1_i64(i64 %index, i64 %TC) {
 define <vscale x 32 x i1> @lane_mask_nxv32i1_i8(i8 %index, i8 %TC) {
 ; CHECK-LABEL: lane_mask_nxv32i1_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    index z0.b, #0, #1
 ; CHECK-NEXT:    rdvl x8, #1
-; CHECK-NEXT:    mov z2.b, w0
-; CHECK-NEXT:    mov z1.b, w8
-; CHECK-NEXT:    ptrue p1.b
-; CHECK-NEXT:    add z1.b, z0.b, z1.b
-; CHECK-NEXT:    uqadd z0.b, z0.b, z2.b
-; CHECK-NEXT:    uqadd z1.b, z1.b, z2.b
-; CHECK-NEXT:    mov z2.b, w1
-; CHECK-NEXT:    cmphi p0.b, p1/z, z2.b, z0.b
-; CHECK-NEXT:    cmphi p1.b, p1/z, z2.b, z1.b
+; CHECK-NEXT:    and w9, w0, #0xff
+; CHECK-NEXT:    mov w10, #255 // =0xff
+; CHECK-NEXT:    add w8, w9, w8, uxtb
+; CHECK-NEXT:    and w11, w1, #0xff
+; CHECK-NEXT:    cmp w8, #255
+; CHECK-NEXT:    csel w8, w8, w10, lo
+; CHECK-NEXT:    whilelo p0.b, w9, w11
+; CHECK-NEXT:    whilelo p1.b, w8, w11
 ; CHECK-NEXT:    ret
   %active.lane.mask = call <vscale x 32 x i1> @llvm.get.active.lane.mask.nxv32i1.i8(i8 %index, i8 %TC)
   ret <vscale x 32 x i1> %active.lane.mask
 }
 
+define <vscale x 7 x i1> @lane_mask_nxv7i1_i64(i64 %index, i64 %TC) {
+; CHECK-LABEL: lane_mask_nxv7i1_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    whilelo p0.h, x0, x1
+; CHECK-NEXT:    ret
+  %active.lane.mask = call <vscale x 7 x i1> @llvm.get.active.lane.mask.nxv7i1.i64(i64 %index, i64 %TC)
+  ret <vscale x 7 x i1> %active.lane.mask
+}
+
+define <vscale x 1 x i1> @lane_mask_nxv1i1_i8(i32 %index, i32 %TC) {
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paulwalker-arm wrote:

lane_mask_nxv1i1_i8 -> lane_mask_nxv1i1_i32?

https://github.com/llvm/llvm-project/pull/140062