[llvm] [AMDGPU][MISched] Allow memory ops of different base pointers to be clustered (PR #140674)

[Matt Arsenault via llvm-commits]

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@@ -585,10 +585,24 @@ bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
     const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
     const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
 
-    if (!DisableDiffBasePtrMemClustering) {
+    if (EnableDiffBasePtrMemClustering) {
       // Only consider memory ops from same addrspace for clustering
       if (!memOpsHaveSameAddrspace(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
         return false;
+
+      // Don't cluster scalar and vecter memory ops
+      const MachineFunction &MF = *FirstLdSt.getParent()->getParent();
+      const MachineRegisterInfo &MRI = MF.getRegInfo();
+      if (FirstLdSt.getOperand(0).isReg() &&
+          SecondLdSt.getOperand(0).isReg()) {
+        bool isFirstVecReg =  RI.isVectorRegister(MRI, 
+            FirstLdSt.getOperand(0).getReg());
+        bool isSecondVecReg = RI.isVectorRegister(MRI,
+            SecondLdSt.getOperand(0).getReg());
+        if ((isFirstVecReg && !isSecondVecReg) || 
+            (!isFirstVecReg && isSecondVecReg))
+          return false;
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arsenm wrote:

You don't need to do the register class check, I would just use isVMEM vs. isSMEM on the instruction 

https://github.com/llvm/llvm-project/pull/140674