[llvm] [RISCV] add Double Trap extensions requires Zicsr (PR #141016)

[Jerry Zhang Jian via llvm-commits]

https://github.com/jerryzj created https://github.com/llvm/llvm-project/pull/141016

- The double trap extension requires `mtval2' register, so add Zicsr as required extension

>From ff1bc131059df6686a7a405e657317688fe3a5b2 Mon Sep 17 00:00:00 2001
From: Jerry Zhang Jian <jerry.zhangjian at sifive.com>
Date: Thu, 22 May 2025 14:59:52 +0800
Subject: [PATCH] [RISCV] add Double Trap extensions requires Zicsr

- The double trap extension requires `mtval2' register, so add Zicsr as required extension

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian at sifive.com>
---
 llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
 llvm/test/CodeGen/RISCV/attributes.ll  | 8 ++++----
 llvm/test/MC/RISCV/attribute-arch.s    | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 28b108c21f385..86576ed190d14 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -922,9 +922,9 @@ def FeatureStdExtSscsrind
     : RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;
 
 def FeatureStdExtSmdbltrp
-    : RISCVExtension<1, 0, "Double Trap Machine Level">;
+    : RISCVExtension<1, 0, "Double Trap Machine Level", [FeatureStdExtZicsr]>;
 def FeatureStdExtSsdbltrp
-    : RISCVExtension<1, 0, "Double Trap Supervisor Level">;
+    : RISCVExtension<1, 0, "Double Trap Supervisor Level", [FeatureStdExtZicsr]>;
 
 def FeatureStdExtSmepmp
     : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index ab73a85bfd7b1..68b472936ecdf 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -496,8 +496,8 @@
 ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
 ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
-; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
-; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
+; RV32SMDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_smdbltrp1p0"
+; RV32SSDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"
 ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
 ; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
@@ -653,8 +653,8 @@
 ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
 ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
-; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
-; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
+; RV64SMDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_smdbltrp1p0"
+; RV64SSDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_ssdbltrp1p0"
 ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
 ; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index d3b49d03279a2..202f54172ca74 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -331,10 +331,10 @@
 # CHECK: attribute      5, "rv32i2p1_sscsrind1p0"
 
 .attribute arch, "rv32i_smdbltrp1p0"
-# CHECK: attribute      5, "rv32i2p1_smdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_smdbltrp1p0"
 
 .attribute arch, "rv32i_ssdbltrp1p0"
-# CHECK: attribute      5, "rv32i2p1_ssdbltrp1p0"
+# CHECK: attribute      5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"
 
 .attribute arch, "rv32i_smcdeleg1p0"
 # CHECK: attribute      5, "rv32i2p1_smcdeleg1p0"