[llvm] [X86][Codegen] add sched for lnlp (PR #139446)

[Haohai Wen via llvm-commits]

HaohaiWen wrote:

Are there new tpt/lat/port info apart from existing schedule model?
I didn't find something like https://www.intel.com/content/www/us/en/content-details/723498/intel-processors-and-processor-cores-based-on-golden-cove-microarchitecture-instruction-throughput-and-latency.html for lioncove.

Is this schedule model verified by llvm-smv (from schedtool)?

https://github.com/llvm/llvm-project/pull/139446