[llvm] [RISCV] Support LLVM IR intrinsics for XAndesVDot (PR #140223)

[Min-Yih Hsu via llvm-commits]

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@@ -0,0 +1,405 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+xandesvdot \
+; RUN:   -verify-machineinstrs -target-abi=ilp32 | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvdot \
+; RUN:   -verify-machineinstrs -target-abi=lp64 | FileCheck %s
+
+declare <vscale x 1 x i32> @llvm.riscv.nds.vd4dots.nxv1i32.nxv4i8.nxv4i8(
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mshockwave wrote:

we no longer need to declare intrinsics

https://github.com/llvm/llvm-project/pull/140223