[llvm] [RISCV] Lower PARTIAL_REDUCE_[S/U]MLA via zvqdotq (PR #140950)

[Philip Reames via llvm-commits]

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@@ -1571,6 +1571,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
     setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
   }
 
+  // zve32x is broken for partial_reduce_umla, but let's not make it worse.
+  if (Subtarget.hasStdExtZvqdotq() && Subtarget.getRealMinVLen() >= 64) {
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preames wrote:

What's the exact check to use here? Is it !Subtarget.hasVInstructionsI64()?

This is hard to check since it fails either way...

https://github.com/llvm/llvm-project/pull/140950