[llvm] [AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg (PR #140946)

[Brox Chen via llvm-commits]

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@@ -16062,7 +16062,10 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
     case 'v':
       switch (BitWidth) {
       case 16:
-        RC = &AMDGPU::VGPR_32RegClass;
+        if (Subtarget->useRealTrue16Insts())
+          RC = &AMDGPU::VGPR_16RegClass;
+        else
+          RC = &AMDGPU::VGPR_32RegClass;
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broxigarchen wrote:

done

https://github.com/llvm/llvm-project/pull/140946