[llvm] 77c8d21 - [GlobalISel] Fix ZExt known bits for scalable vectors. (#140213)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 21 11:52:23 PDT 2025
Author: David Green
Date: 2025-05-21T19:52:19+01:00
New Revision: 77c8d214131e951e3d3a07b45a7436f54988d6f3
URL: https://github.com/llvm/llvm-project/commit/77c8d214131e951e3d3a07b45a7436f54988d6f3
DIFF: https://github.com/llvm/llvm-project/commit/77c8d214131e951e3d3a07b45a7436f54988d6f3.diff
LOG: [GlobalISel] Fix ZExt known bits for scalable vectors. (#140213)
It was using the full size of the vector as the SrcBitWidth. This patch
changes the code to split G_ASSERT_ZEXT away from the others (G_INTTOPTR
/ G_PTRTOINT / G_ZEXT / G_TRUNC) which are simpler, and make the code
match the SDAG equivalent.
Added:
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir
Modified:
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 99794d690a91c..d16eef1178cbc 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -481,27 +481,22 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
break;
// Fall through and handle them the same as zext/trunc.
[[fallthrough]];
- case TargetOpcode::G_ASSERT_ZEXT:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_TRUNC: {
Register SrcReg = MI.getOperand(1).getReg();
- LLT SrcTy = MRI.getType(SrcReg);
- unsigned SrcBitWidth;
-
- // G_ASSERT_ZEXT stores the original bitwidth in the immediate operand.
- if (Opcode == TargetOpcode::G_ASSERT_ZEXT)
- SrcBitWidth = MI.getOperand(2).getImm();
- else {
- SrcBitWidth = SrcTy.isPointer()
- ? DL.getIndexSizeInBits(SrcTy.getAddressSpace())
- : SrcTy.getSizeInBits();
- }
- assert(SrcBitWidth && "SrcBitWidth can't be zero");
- Known = Known.zextOrTrunc(SrcBitWidth);
computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
Known = Known.zextOrTrunc(BitWidth);
- if (BitWidth > SrcBitWidth)
- Known.Zero.setBitsFrom(SrcBitWidth);
+ break;
+ }
+ case TargetOpcode::G_ASSERT_ZEXT: {
+ Register SrcReg = MI.getOperand(1).getReg();
+ computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1);
+
+ unsigned SrcBitWidth = MI.getOperand(2).getImm();
+ assert(SrcBitWidth && "SrcBitWidth can't be zero");
+ APInt InMask = APInt::getLowBitsSet(BitWidth, SrcBitWidth);
+ Known.Zero |= (~InMask);
+ Known.One &= (~Known.Zero);
break;
}
case TargetOpcode::G_ASSERT_ALIGN: {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir
new file mode 100644
index 0000000000000..9b2089f17dea4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-assertzext.mir
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -mattr=+sve -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+---
+name: ScalarConst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarConst
+ ; CHECK-NEXT: %0:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ %0:_(s32) = G_CONSTANT i32 120
+ %1:_(s32) = G_ASSERT_ZEXT %0(s32), 16
+...
+---
+name: ScalarVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = G_ASSERT_ZEXT %0(s32), 16
+...
+---
+name: VectorCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorCst
+ ; CHECK-NEXT: %0:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ %0:_(s32) = G_CONSTANT i32 120
+ %1:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %2:_(<4 x s32>) = G_ASSERT_ZEXT %1(<4 x s32>), 16
+...
+---
+name: VectorVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s32>) = G_ASSERT_ZEXT %0(<4 x s32>), 16
+...
+---
+name: ScalableCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableCst
+ ; CHECK-NEXT: %0:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000001111000 SignBits:25
+ %0:_(s32) = G_CONSTANT i32 120
+ %1:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %0
+ %2:_(<vscale x 4 x s32>) = G_ASSERT_ZEXT %1(<vscale x 4 x s32>), 16
+...
+---
+name: ScalableVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(<vscale x 4 x s32>) = COPY $z0
+ %1:_(<vscale x 4 x s32>) = G_ASSERT_ZEXT %0(<vscale x 4 x s32>), 16
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir
new file mode 100644
index 0000000000000..f680196a4225e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-trunk.mir
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+---
+name: ScalarConst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarConst
+ ; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0110010101000011 SignBits:1
+ %0:_(s32) = G_CONSTANT i32 2844222787
+ %1:_(s16) = G_TRUNC %0(s32)
+...
+---
+name: ScalarVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ %0:_(s32) = COPY $w0
+ %1:_(s16) = G_TRUNC %0(s32)
+...
+---
+name: VectorCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorCst
+ ; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:10101001100001110110010101000011 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0110010101000011 SignBits:1
+ %0:_(s32) = G_CONSTANT i32 2844222787
+ %1:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %2:_(<4 x s16>) = G_TRUNC %1(<4 x s32>)
+...
+---
+name: VectorVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ %0:_(<4 x s32>) = COPY $q0
+ %1:_(<4 x s16>) = G_TRUNC %0(<4 x s32>)
+...
+---
+name: ScalableCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableCst
+ ; CHECK-NEXT: %0:_ KnownBits:10101001100001110110010101000011 SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:10101001100001110110010101000011 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0110010101000011 SignBits:1
+ %0:_(s32) = G_CONSTANT i32 2844222787
+ %1:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %0
+ %2:_(<vscale x 4 x s16>) = G_TRUNC %1(<vscale x 4 x s32>)
+...
+---
+name: ScalableVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ %0:_(<vscale x 4 x s32>) = COPY $z0
+ %1:_(<vscale x 4 x s16>) = G_TRUNC %0(<vscale x 4 x s32>)
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir
new file mode 100644
index 0000000000000..a420ff669b3d3
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-zext.mir
@@ -0,0 +1,67 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -mattr=+sve -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
+
+---
+name: ScalarConst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarConst
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001010 SignBits:28
+ %0:_(s16) = G_CONSTANT i16 10
+ %1:_(s32) = G_ZEXT %0(s16)
+...
+---
+name: ScalarVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(s16) = COPY $h0
+ %1:_(s32) = G_ZEXT %0(s16)
+...
+---
+name: VectorCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorCst
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000001010 SignBits:12
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000001010 SignBits:28
+ %0:_(s16) = G_CONSTANT i16 10
+ %1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0
+ %2:_(<4 x s32>) = G_ZEXT %1(<4 x s16>)
+...
+---
+name: VectorVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
+...
+---
+name: ScalableCst
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableCst
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000001010 SignBits:12
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000001010 SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000000000001010 SignBits:28
+ %0:_(s16) = G_CONSTANT i16 10
+ %1:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %0
+ %2:_(<vscale x 4 x s32>) = G_ZEXT %1(<vscale x 4 x s16>)
+...
+---
+name: ScalableVar
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @ScalableVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000000???????????????? SignBits:16
+ %0:_(<vscale x 4 x s16>) = COPY $z0
+ %1:_(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>)
+...
More information about the llvm-commits
mailing list