[llvm] 91b2e5b - Add live in for PrivateSegmentSize in GISel path (#139968)

via llvm-commits llvm-commits at lists.llvm.org
Wed May 21 09:25:28 PDT 2025


Author: Jake Daly
Date: 2025-05-21T18:25:25+02:00
New Revision: 91b2e5bc5d3bcad511f3dfd90e1cedf796218675

URL: https://github.com/llvm/llvm-project/commit/91b2e5bc5d3bcad511f3dfd90e1cedf796218675
DIFF: https://github.com/llvm/llvm-project/commit/91b2e5bc5d3bcad511f3dfd90e1cedf796218675.diff

LOG: Add live in for PrivateSegmentSize in GISel path (#139968)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index e977b9069173e..98a32f9225ba9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -493,6 +493,12 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
     CCInfo.AllocateReg(FlatScratchInitReg);
   }
 
+  if (UserSGPRInfo.hasPrivateSegmentSize()) {
+    Register PrivateSegmentSizeReg = Info.addPrivateSegmentSize(TRI);
+    MF.addLiveIn(PrivateSegmentSizeReg, &AMDGPU::SGPR_32RegClass);
+    CCInfo.AllocateReg(PrivateSegmentSizeReg);
+  }
+
   // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
   // these from the dispatch pointer.
 }


        


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