[llvm] [RISCV] Add a pass to eliminate special copies in order to facilitate shrink-wrap optimization (PR #140716)

[Craig Topper via llvm-commits]

topperc wrote:

> I did some more digging of where these copies come from. At least for the test case from shrinkwrap.ll, the copy is created by a CopyToReg that is inserted after the AssertZExt from argument lowering. This copy is not created for this test case on RV32 because the AssertZExt doesn't get created and there's a peephole that avoids creating a CopyToReg if the the source is a CopyFromReg here https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L11882
> 
> In order to for SelectionDAG's cross basic block known bits propagation to work we do need this CopyToReg to propagate the AssertZExt information. After the last DAGCombine we call computeKnownBits on all CopyToReg node inputs and save the KnownBits in a map entry for the destination register. This map is queried by SelectionDAGBuilder for the CopyFromReg in the receiving block.
> 
> I wonder if we can avoid creating the CopyToReg by peeking through the AssertZExt around here https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L11882, but update the KnownBits cache.

I think I've completely misunderstood. This pass is exploiting the existence of the extra copy and removing it in a different way than the register coalescer does. The shrink-wrap problem still exists for this case in RV32 and would exist for an i64 argument on RV64.

https://github.com/llvm/llvm-project/pull/140716