[llvm] [AMDGPU][MISched] Allow memory ops of different base pointers to be clustered (PR #140674)

[Matt Arsenault via llvm-commits]

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@@ -288,16 +288,16 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr)  #0 {
 ; GFX8V4-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8V4-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8V4-NEXT:    flat_load_ubyte v0, v[0:1] glc
+; GFX8V4-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
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arsenm wrote:

Do we still want this to apply to clustering mixed scalar and vector loads? They can't be claused together and have different top level caches 

https://github.com/llvm/llvm-project/pull/140674