[llvm] [AArch64][SDAG] Fix selection of extend of v1if16 SETCC (PR #140274)

[Matt Arsenault via llvm-commits]

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@@ -6623,8 +6623,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
     InOp1 = GetWidenedVector(InOp1);
     InOp2 = GetWidenedVector(InOp2);
   } else {
-    InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
-    InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
+    SDValue Undef = DAG.getUNDEF(WidenInVT);
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arsenm wrote:

Probably should be poison 

https://github.com/llvm/llvm-project/pull/140274