[llvm] [AArch64][SDAG] Fix selection of extend of v1if16 SETCC (PR #140274)

[David Green via llvm-commits]

davemgreen wrote:

> It seems like this was deliberately done back in https://reviews.llvm.org/D4322 (apparently to avoid some legalization issues).

Oh - it was setcc specifically I was thinking of, not all operations. setcc is a little odd because the return type is comparatively less important to the type of the operands, which specifies whether the operation is float or integer.

If the DAG combine that creates the v1i16 is the transform that is causing this to go wrong then maybe it would be better to disable it somehow. It should be possible to mark that specific type as v1i1 in getSetCCResultType to encourage it to scalarize instead. The vector codegen isn't as efficient as it could be so maybe it doesn't matter a lot whether we scalarize or not, and your explanation as to what goes wrong makes sense.

https://github.com/llvm/llvm-project/pull/140274