[llvm] [RISCV] Add Xqcibi Select_GPR_Using_CC_<Imm> Pseudos to isSelectPseudo (PR #140698)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Tue May 20 21:23:18 PDT 2025
https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/140698
>From d267c8262a392febb0030d29d33f73765b7e9bfb Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Tue, 20 May 2025 14:36:52 +0530
Subject: [PATCH 1/2] [RISCV] Select_CC
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ++++-
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 8 +++---
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 16 +++++------
llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 4 +++
llvm/test/CodeGen/RISCV/xqcibi.ll | 27 +++++++++++++++++++
6 files changed, 49 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1158499718737..5f9e3f2080683 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21018,7 +21018,11 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5) &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5 &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm16NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm16NonZero) &&
Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
Next->getOperand(5).isKill())
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 41b3a57315b57..84b1e639cee35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1646,12 +1646,12 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
def : SelectCompressOpt<SETNE>;
}
-multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
+multiclass SelectCC_GPR_riirr<DAGOperand outvalty, DAGOperand invalty, DAGOperand imm> {
let usesCustomInserter = 1 in
def Select_GPR_Using_ # NAME
- : Pseudo<(outs valty:$dst),
- (ins GPR:$lhs, imm:$imm, cond_code:$cc,
- valty:$truev, valty:$falsev), []>;
+ : Pseudo<(outs outvalty:$dst),
+ (ins invalty:$lhs, imm:$imm, cond_code:$cc,
+ outvalty:$truev, outvalty:$falsev), []>;
}
/// Branches and jumps
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 2b068e66bcf21..f735e2b3e57c0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -802,7 +802,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
- defm CC_SImm5 : SelectCC_GPR_riirr<GPR, simm5>;
+ defm CC_SImm5 : SelectCC_GPR_riirr<GPR, GPR, simm5>;
class Selectbi<CondCode Cond>
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 04db0fd07f109..4ac952ef121b2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1327,16 +1327,16 @@ class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
-defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPR, simm5nonzero>;
-defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPR, uimm5nonzero>;
-defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPR, simm16nonzero>;
-defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPR, uimm16nonzero>;
+defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm5nonzero>;
+defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm5nonzero>;
+defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm16nonzero>;
+defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm16nonzero>;
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
- : Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
- (i32 GPR:$truev), GPR:$falsev),
- (OpNode GPR:$lhs, InTyImm:$Constant,
- (IntCCtoQCRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
+ : Pat<(riscv_selectcc_frag:$cc (i32 GPRNoX0:$lhs), InTyImm:$Constant, Cond,
+ (i32 GPRNoX0:$truev), GPRNoX0:$falsev),
+ (OpNode GPRNoX0:$lhs, InTyImm:$Constant,
+ (IntCCtoQCRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;
/// Simple arithmetic operations
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 5056f6f5baf4d..d8b1a5d8dc14a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -50,6 +50,10 @@ def isSelectPseudo
CheckOpcode<[
Select_GPR_Using_CC_GPR,
Select_GPR_Using_CC_SImm5,
+ Select_GPR_Using_CC_SImm5NonZero,
+ Select_GPR_Using_CC_UImm5NonZero,
+ Select_GPR_Using_CC_SImm16NonZero,
+ Select_GPR_Using_CC_UImm16NonZero,
Select_FPR16_Using_CC_GPR,
Select_FPR16INX_Using_CC_GPR,
Select_FPR32_Using_CC_GPR,
diff --git a/llvm/test/CodeGen/RISCV/xqcibi.ll b/llvm/test/CodeGen/RISCV/xqcibi.ll
index 242012b5ad462..f628e0086374c 100644
--- a/llvm/test/CodeGen/RISCV/xqcibi.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibi.ll
@@ -355,5 +355,32 @@ t:
ret i32 1
}
+define i1 @selectcc(i64 %0) {
+; RV32I-LABEL: selectcc:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a2, 512
+; RV32I-NEXT: beq a1, a2, .LBB12_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: sltiu a0, a1, 513
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB12_2:
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: ret
+;
+; RV32IXQCIBI-LABEL: selectcc:
+; RV32IXQCIBI: # %bb.0: # %entry
+; RV32IXQCIBI-NEXT: qc.e.beqi a1, 512, .LBB12_2
+; RV32IXQCIBI-NEXT: # %bb.1: # %entry
+; RV32IXQCIBI-NEXT: sltiu a0, a1, 513
+; RV32IXQCIBI-NEXT: xori a0, a0, 1
+; RV32IXQCIBI-NEXT: ret
+; RV32IXQCIBI-NEXT: .LBB12_2:
+; RV32IXQCIBI-NEXT: snez a0, a0
+; RV32IXQCIBI-NEXT: ret
+entry:
+ %cmp10.i = icmp ugt i64 %0, 2199023255552
+ ret i1 %cmp10.i
+}
!0 = !{!"branch_weights", i32 1, i32 99}
>From 673622d4280cee67b44d0466e2d52b7fc69abd30 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Wed, 21 May 2025 09:52:47 +0530
Subject: [PATCH 2/2] Use valtype and vendor prefix in variables
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 20 +++++------
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 10 +++---
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 4 +--
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 34 +++++++++----------
llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 10 +++---
5 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5f9e3f2080683..b70b20140cd93 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21018,11 +21018,11 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5 &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5NonZero &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm5NonZero &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm16NonZero &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm16NonZero) &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CV_CC_SImm5 &&
+ MI.getOpcode() != RISCV::Select_GPRNoX0_Using_QC_CC_SImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPRNoX0_Using_QC_CC_UImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPRNoX0_Using_QC_CC_SImm16NonZero &&
+ MI.getOpcode() != RISCV::Select_GPRNoX0_Using_QC_CC_UImm16NonZero) &&
Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
Next->getOperand(5).isKill())
@@ -21355,11 +21355,11 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
"ReadCounterWide is only to be used on riscv32");
return emitReadCounterWidePseudo(MI, BB);
case RISCV::Select_GPR_Using_CC_GPR:
- case RISCV::Select_GPR_Using_CC_SImm5:
- case RISCV::Select_GPR_Using_CC_SImm5NonZero:
- case RISCV::Select_GPR_Using_CC_UImm5NonZero:
- case RISCV::Select_GPR_Using_CC_SImm16NonZero:
- case RISCV::Select_GPR_Using_CC_UImm16NonZero:
+ case RISCV::Select_GPR_Using_CV_CC_SImm5:
+ case RISCV::Select_GPRNoX0_Using_QC_CC_SImm5NonZero:
+ case RISCV::Select_GPRNoX0_Using_QC_CC_UImm5NonZero:
+ case RISCV::Select_GPRNoX0_Using_QC_CC_SImm16NonZero:
+ case RISCV::Select_GPRNoX0_Using_QC_CC_UImm16NonZero:
case RISCV::Select_FPR16_Using_CC_GPR:
case RISCV::Select_FPR16INX_Using_CC_GPR:
case RISCV::Select_FPR32_Using_CC_GPR:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 84b1e639cee35..d0ea753a7e1df 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1646,12 +1646,12 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
def : SelectCompressOpt<SETNE>;
}
-multiclass SelectCC_GPR_riirr<DAGOperand outvalty, DAGOperand invalty, DAGOperand imm> {
+multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
let usesCustomInserter = 1 in
- def Select_GPR_Using_ # NAME
- : Pseudo<(outs outvalty:$dst),
- (ins invalty:$lhs, imm:$imm, cond_code:$cc,
- outvalty:$truev, outvalty:$falsev), []>;
+ def Select_# valty #_Using_ # NAME
+ : Pseudo<(outs valty:$dst),
+ (ins valty:$lhs, imm:$imm, cond_code:$cc,
+ valty:$truev, valty:$falsev), []>;
}
/// Branches and jumps
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index f735e2b3e57c0..2d745e2ecd596 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -802,12 +802,12 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
- defm CC_SImm5 : SelectCC_GPR_riirr<GPR, GPR, simm5>;
+ defm CV_CC_SImm5 : SelectCC_GPR_riirr<GPR, simm5>;
class Selectbi<CondCode Cond>
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
(i32 GPR:$truev), GPR:$falsev),
- (Select_GPR_Using_CC_SImm5 GPR:$lhs, simm5:$Constant,
+ (Select_GPR_Using_CV_CC_SImm5 GPR:$lhs, simm5:$Constant,
(IntCCtoRISCVCCCV $cc), GPR:$truev, GPR:$falsev)>;
def : Selectbi<SETEQ>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 4ac952ef121b2..4c3fe9e03a8dc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1327,10 +1327,10 @@ class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
-defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm5nonzero>;
-defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm5nonzero>;
-defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm16nonzero>;
-defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm16nonzero>;
+defm QC_CC_SImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, simm5nonzero>;
+defm QC_CC_UImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, uimm5nonzero>;
+defm QC_CC_SImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, simm16nonzero>;
+defm QC_CC_UImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, uimm16nonzero>;
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
: Pat<(riscv_selectcc_frag:$cc (i32 GPRNoX0:$lhs), InTyImm:$Constant, Cond,
@@ -1409,19 +1409,19 @@ def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
-def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
-def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
-def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
-def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
-def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
-def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
-
-def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
-def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
-def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
-def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
-def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
-def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
+def : SelectQCbi<SETEQ, simm5nonzero, Select_GPRNoX0_Using_QC_CC_SImm5NonZero>;
+def : SelectQCbi<SETNE, simm5nonzero, Select_GPRNoX0_Using_QC_CC_SImm5NonZero>;
+def : SelectQCbi<SETLT, simm5nonzero, Select_GPRNoX0_Using_QC_CC_SImm5NonZero>;
+def : SelectQCbi<SETGE, simm5nonzero, Select_GPRNoX0_Using_QC_CC_SImm5NonZero>;
+def : SelectQCbi<SETULT, uimm5nonzero, Select_GPRNoX0_Using_QC_CC_UImm5NonZero>;
+def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPRNoX0_Using_QC_CC_UImm5NonZero>;
+
+def : SelectQCbi<SETEQ, simm16nonzero, Select_GPRNoX0_Using_QC_CC_SImm16NonZero>;
+def : SelectQCbi<SETNE, simm16nonzero, Select_GPRNoX0_Using_QC_CC_SImm16NonZero>;
+def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_QC_CC_SImm16NonZero>;
+def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_QC_CC_SImm16NonZero>;
+def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_QC_CC_UImm16NonZero>;
+def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_QC_CC_UImm16NonZero>;
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
let Predicates = [HasVendorXqcibm, IsRV32] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index d8b1a5d8dc14a..25f591b556dd0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -49,11 +49,11 @@ def isSelectPseudo
MCReturnStatement<
CheckOpcode<[
Select_GPR_Using_CC_GPR,
- Select_GPR_Using_CC_SImm5,
- Select_GPR_Using_CC_SImm5NonZero,
- Select_GPR_Using_CC_UImm5NonZero,
- Select_GPR_Using_CC_SImm16NonZero,
- Select_GPR_Using_CC_UImm16NonZero,
+ Select_GPR_Using_CV_CC_SImm5,
+ Select_GPRNoX0_Using_QC_CC_SImm5NonZero,
+ Select_GPRNoX0_Using_QC_CC_UImm5NonZero,
+ Select_GPRNoX0_Using_QC_CC_SImm16NonZero,
+ Select_GPRNoX0_Using_QC_CC_UImm16NonZero,
Select_FPR16_Using_CC_GPR,
Select_FPR16INX_Using_CC_GPR,
Select_FPR32_Using_CC_GPR,
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