[lld] [llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)
Arjun Patel via llvm-commits
llvm-commits at lists.llvm.org
Tue May 20 21:03:35 PDT 2025
https://github.com/arjunUpatel updated https://github.com/llvm/llvm-project/pull/109914
>From a46dd9231d3a175f4f4a6e28cc6146cc5f4ec6eb Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Wed, 25 Sep 2024 00:59:45 -0400
Subject: [PATCH 01/32] added evaluateInstruction method. needs tests
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 4 ++
llvm/lib/MC/MCInstrAnalysis.cpp | 7 ++
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 69 +++++++++++++++----
llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +-
4 files changed, 67 insertions(+), 15 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index b571791c518da..7a0085268727a 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -181,6 +181,10 @@ class MCInstrAnalysis {
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;
+ virtual bool
+ evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const;
+
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
virtual std::optional<uint64_t>
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index cea905d092e0b..de1319698f966 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -10,6 +10,7 @@
#include "llvm/ADT/APInt.h"
#include <cstdint>
+#include "MCInstrAnalysis.h"
namespace llvm {
class MCSubtargetInfo;
@@ -30,6 +31,12 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
return false;
}
+bool llvm::MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
+ uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const {
+ return false;
+}
+
std::optional<uint64_t> MCInstrAnalysis::evaluateMemoryOperandAddress(
const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
uint64_t Size) const {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index a0dc9d93c84b8..73d975bf3d6a3 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -178,21 +178,24 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
- default: {
- // Clear the state of all defined registers for instructions that we don't
- // explicitly support.
- auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
- for (unsigned I = 0; I < NumDefs; ++I) {
- auto DefReg = Inst.getOperand(I).getReg();
- if (isGPR(DefReg))
- setGPRState(DefReg, std::nullopt);
+ default: {
+ // Clear the state of all defined registers for instructions that we don't
+ // explicitly support.
+ auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
+ for (unsigned I = 0; I < NumDefs; ++I) {
+ auto DefReg = Inst.getOperand(I).getReg();
+ if (isGPR(DefReg))
+ setGPRState(DefReg, std::nullopt);
+ }
+ break;
+ }
+ case RISCV::AUIPC:
+ case RISCV::LUI:
+ {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Inst.getOperand(1).getImm() << 12);
+ break;
}
- break;
- }
- case RISCV::AUIPC:
- setGPRState(Inst.getOperand(0).getReg(),
- Addr + (Inst.getOperand(1).getImm() << 12));
- break;
}
}
@@ -230,6 +233,44 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
return false;
}
+ bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const override {
+ switch(Inst.getOpcode()) {
+ default:
+ return false;
+ case RISCV::ADDI:
+ case RISCV::ADDIW: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
+ }
+ break;
+ }
+ case RISCV::LB:
+ case RISCV::LH:
+ case RISCV::LW:
+ case RISCV::LBU:
+ case RISCV::LHU:
+ case RISCV::LWU:
+ case RISCV::LD:
+ case RISCV::FLW:
+ case RISCV::FLD:
+ case RISCV::SB:
+ case RISCV::SH:
+ case RISCV::SW:
+ case RISCV::FSW:
+ case RISCV::SD:
+ case RISCV::FSD: {
+ int64_t Offset = Inst.getOperand(2).getImm();
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
+ Target = *TargetRegState + Offset;
+ else
+ Target = Offset;
+ return true;
+ }
+ }
+ }
+
bool isTerminator(const MCInst &Inst) const override {
if (MCInstrAnalysis::isTerminator(Inst))
return true;
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index b69d14b4e7609..915394fc3b372 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1513,7 +1513,7 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
if (MIA) {
if (Disassembled) {
uint64_t Target;
- bool TargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
+ bool TargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target) || MIA->evaluateInstruction(Inst, Index, Size, Target);
if (TargetKnown && (Target >= Start && Target < End) &&
!Labels.count(Target)) {
// On PowerPC and AIX, a function call is encoded as a branch to 0.
>From 30dd584dc7ec6e4c162aecd3e0ddcb906b9d6374 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Wed, 25 Sep 2024 03:26:15 -0400
Subject: [PATCH 02/32] dealing with git
---
llvm/lib/MC/MCInstrAnalysis.cpp | 3 +--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 9 ++++++---
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index de1319698f966..49acfbbfcc659 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -10,7 +10,6 @@
#include "llvm/ADT/APInt.h"
#include <cstdint>
-#include "MCInstrAnalysis.h"
namespace llvm {
class MCSubtargetInfo;
@@ -31,7 +30,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
return false;
}
-bool llvm::MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
+bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
uint64_t Addr, uint64_t Size,
uint64_t &Target) const {
return false;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 73d975bf3d6a3..e431fa1014d5e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -189,9 +189,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
break;
}
- case RISCV::AUIPC:
- case RISCV::LUI:
- {
+ case RISCV::AUIPC: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + (Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ case RISCV::LUI: {
setGPRState(Inst.getOperand(0).getReg(),
Inst.getOperand(1).getImm() << 12);
break;
>From fce36f154b413dbfa2c4a8da7d6b9ee7211180f8 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Sun, 13 Oct 2024 22:24:56 -0400
Subject: [PATCH 03/32] sign extend relevant immediates
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 51 +++++++++++++------
llvm/tools/llvm-objdump/llvm-objdump.cpp | 22 +++++---
2 files changed, 50 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index e431fa1014d5e..6325b5bd594de 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -31,7 +31,9 @@
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include <bitset>
+#include <cstdint>
#define GET_INSTRINFO_MC_DESC
#define ENABLE_INSTR_PREDICATE_VERIFIER
@@ -178,6 +180,24 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
+ case RISCV::LUI: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ case RISCV::C_LUI: {
+ MCRegister Reg = Inst.getOperand(0).getReg();
+ if (Reg == RISCV::X2)
+ break;
+ setGPRState(Reg, SignExtend64<17>(Inst.getOperand(1).getImm() << 12));
+ break;
+
+ }
+ case RISCV::AUIPC: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
default: {
// Clear the state of all defined registers for instructions that we don't
// explicitly support.
@@ -189,16 +209,6 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
break;
}
- case RISCV::AUIPC: {
- setGPRState(Inst.getOperand(0).getReg(),
- Addr + (Inst.getOperand(1).getImm() << 12));
- break;
- }
- case RISCV::LUI: {
- setGPRState(Inst.getOperand(0).getReg(),
- Inst.getOperand(1).getImm() << 12);
- break;
- }
}
}
@@ -244,34 +254,43 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::ADDI:
case RISCV::ADDIW: {
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- Target = *TargetRegState + Inst.getOperand(2).getImm();
+ // TODO: Figure out ways to find the actual value of XLEN during analysis
+ int XLEN = 32;
+ uint64_t mask = ~(0) >> XLEN;
+ Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
+ Target &= mask;
+ Target = SignExtend64<32>(Target);
return true;
}
break;
}
case RISCV::LB:
case RISCV::LH:
+ case RISCV::LD:
case RISCV::LW:
case RISCV::LBU:
case RISCV::LHU:
case RISCV::LWU:
- case RISCV::LD:
- case RISCV::FLW:
- case RISCV::FLD:
case RISCV::SB:
case RISCV::SH:
case RISCV::SW:
- case RISCV::FSW:
case RISCV::SD:
+ case RISCV::FLH:
+ case RISCV::FLW:
+ case RISCV::FLD:
+ case RISCV::FSH:
+ case RISCV::FSW:
case RISCV::FSD: {
- int64_t Offset = Inst.getOperand(2).getImm();
+ int64_t Offset = SignExtend64<12>(Inst.getOperand(2).getImm());
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
Target = *TargetRegState + Offset;
else
Target = Offset;
return true;
}
+ // TODO: Add cases for compressed load and store instructions
}
+ return false;
}
bool isTerminator(const MCInst &Inst) const override {
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 915394fc3b372..f2199f8e5b486 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1513,9 +1513,8 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
if (MIA) {
if (Disassembled) {
uint64_t Target;
- bool TargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target) || MIA->evaluateInstruction(Inst, Index, Size, Target);
- if (TargetKnown && (Target >= Start && Target < End) &&
- !Labels.count(Target)) {
+ bool BranchTargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
+ if (BranchTargetKnown && (Target >= Start && Target < End)) {
// On PowerPC and AIX, a function call is encoded as a branch to 0.
// On other PowerPC platforms (ELF), a function call is encoded as
// a branch to self. Do not add a label for these cases.
@@ -2322,8 +2321,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
- Inst, SectionAddr + Index, Size, Target);
+ bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
@@ -2397,7 +2396,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
break;
}
- // Branch targets are printed just after the instructions.
+ // Branch and instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
bool BBAddrMapLabelAvailable = BBAddrMapLabels.count(Target);
bool LabelAvailable = AllLabels.count(Target);
@@ -2478,7 +2477,16 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
<< ">";
} else if (LabelAvailable) {
*TargetOS << " <" << AllLabels[Target] << ">";
- }
+ }
+ // else {
+ // this case is needed because the first load in the test assembly
+ // did not have any symbols in the section nor was it caught by any of
+ // else if cases. this warrented a case where the address is printed realtive
+ // to the target section. Since no symbol was found, there is no need to handle
+ // relocations
+ // *TargetOS << " <" <<
+
+ // }
// By convention, each record in the comment stream should be
// terminated.
if (TargetOS == &CommentStream)
>From 4c8d76967645eb85c98af16bcd9bd60e1d6daf48 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 15 Oct 2024 14:14:07 -0400
Subject: [PATCH 04/32] fix indentation
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 2 +-
llvm/lib/MC/MCInstrAnalysis.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 7a0085268727a..71d55d4399cd6 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -183,7 +183,7 @@ class MCInstrAnalysis {
virtual bool
evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const;
+ uint64_t &Target) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 49acfbbfcc659..da7127092b408 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -31,8 +31,8 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
}
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
- uint64_t Addr, uint64_t Size,
- uint64_t &Target) const {
+ uint64_t Addr, uint64_t Size,
+ uint64_t &Target) const {
return false;
}
>From 81e6acdc94ae3f846a11bb440ca7bbadf860585c Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 15 Oct 2024 14:15:47 -0400
Subject: [PATCH 05/32] fix ADDI + sign extention bugs
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 20 +++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 6325b5bd594de..69d6c6cc8e3fc 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -189,7 +189,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
MCRegister Reg = Inst.getOperand(0).getReg();
if (Reg == RISCV::X2)
break;
- setGPRState(Reg, SignExtend64<17>(Inst.getOperand(1).getImm() << 12));
+ setGPRState(Reg, SignExtend64<18>(Inst.getOperand(1).getImm() << 12));
break;
}
@@ -247,18 +247,26 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target) const override {
switch(Inst.getOpcode()) {
default:
return false;
- case RISCV::ADDI:
- case RISCV::ADDIW: {
+ case RISCV::ADDI: {
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
// TODO: Figure out ways to find the actual value of XLEN during analysis
int XLEN = 32;
- uint64_t mask = ~(0) >> XLEN;
+ uint64_t Mask = ~((uint64_t)0) >> (64 - XLEN);
+ Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
+ Target &= Mask;
+ return true;
+ }
+ break;
+ }
+ case RISCV::ADDIW: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ uint64_t Mask = ~((uint64_t)0) >> 32;
Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
- Target &= mask;
+ Target &= Mask;
Target = SignExtend64<32>(Target);
return true;
}
>From c31baef522144f8211fd2d3288e8e11a027390de Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 15 Oct 2024 14:51:21 -0400
Subject: [PATCH 06/32] prevent symbol reoslution in empty sections
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index f2199f8e5b486..eeb9f376c143f 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2366,6 +2366,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (It->first != TargetSecAddr)
break;
TargetSectionSymbols.push_back(&AllSymbols[It->second]);
+ if (AllSymbols[It->second].empty())
+ TargetSecAddr = 0;
}
} else {
TargetSectionSymbols.push_back(&Symbols);
@@ -2478,15 +2480,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
} else if (LabelAvailable) {
*TargetOS << " <" << AllLabels[Target] << ">";
}
- // else {
- // this case is needed because the first load in the test assembly
- // did not have any symbols in the section nor was it caught by any of
- // else if cases. this warrented a case where the address is printed realtive
- // to the target section. Since no symbol was found, there is no need to handle
- // relocations
- // *TargetOS << " <" <<
-
- // }
// By convention, each record in the comment stream should be
// terminated.
if (TargetOS == &CommentStream)
>From de457f9c047aade5b0bc175479fb1799394ccead Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Sun, 20 Oct 2024 14:35:00 -0400
Subject: [PATCH 07/32] added support for compressed instructions
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 38 ++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 69d6c6cc8e3fc..a4e1d68beb534 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -272,6 +272,29 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
break;
}
+ case RISCV::C_ADDI: {
+ int64_t Offset = Inst.getOperand(2).getImm();
+ if (Offset == 0)
+ break;
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + SignExtend64<6>(Offset);
+ return true;
+ }
+ break;
+ }
+ case RISCV::C_ADDIW: {
+ int64_t Offset = Inst.getOperand(2).getImm();
+ if (Offset == 0)
+ break;
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ uint64_t Mask = ~((uint64_t)0) >> 32;
+ Target &= Mask;
+ Target = *TargetRegState + SignExtend64<6>(Offset);
+ Target = SignExtend64<32>(Target);
+ return true;
+ }
+ break;
+ }
case RISCV::LB:
case RISCV::LH:
case RISCV::LD:
@@ -296,7 +319,20 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
Target = Offset;
return true;
}
- // TODO: Add cases for compressed load and store instructions
+ case RISCV::C_LD:
+ case RISCV::C_SD:
+ case RISCV::C_FLD:
+ case RISCV::C_FSD:
+ case RISCV::C_SW:
+ case RISCV::C_LW:
+ case RISCV::C_FSW:
+ case RISCV::C_FLW: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
+ }
+ break;
+ }
}
return false;
}
>From ecfcf565cad6747a72759e715878185f3d616225 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Sun, 20 Oct 2024 17:26:16 -0400
Subject: [PATCH 08/32] call evaluateInstruction only when target=RISCV
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index fab4651521e67..3f332f7db17e9 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2322,9 +2322,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
-
+ bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target);
+ if (DT->SubtargetInfo->getTargetTriple().isRISCV())
+ PrintTarget = DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 33e100edfa55376b39eceb73d0ff04a0990282c8 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 21 Oct 2024 16:03:41 -0400
Subject: [PATCH 09/32] fix bug cause test failures with build
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 3f332f7db17e9..871efe62f9de2 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1514,7 +1514,8 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
if (Disassembled) {
uint64_t Target;
bool BranchTargetKnown = MIA->evaluateBranch(Inst, Index, Size, Target);
- if (BranchTargetKnown && (Target >= Start && Target < End)) {
+ if (BranchTargetKnown && (Target >= Start && Target < End) &&
+ !Labels.count(Target)) {
// On PowerPC and AIX, a function call is encoded as a branch to 0.
// On other PowerPC platforms (ELF), a function call is encoded as
// a branch to self. Do not add a label for these cases.
@@ -2322,9 +2323,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target);
- if (DT->SubtargetInfo->getTargetTriple().isRISCV())
- PrintTarget = DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
+ bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 3fc4e31d140067a5fe1cdd7340494403d912edaa Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 19 Nov 2024 12:46:01 -0500
Subject: [PATCH 10/32] Instr eval based on reg width and attempt to pass tests
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 4 ++-
llvm/lib/MC/MCInstrAnalysis.cpp | 2 +-
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 6 ++--
llvm/tools/llvm-objdump/llvm-objdump.cpp | 29 +++++++++++++------
4 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 71d55d4399cd6..1c32d4177effb 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -181,9 +181,11 @@ class MCInstrAnalysis {
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;
+ /// Given an instruction that accesses a menory address, try to compute
+ /// the target address. Return true success, and the address in Target.
virtual bool
evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const;
+ uint64_t &Target, int ArchRegWidth) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index da7127092b408..41a55637527da 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -32,7 +32,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
uint64_t Addr, uint64_t Size,
- uint64_t &Target) const {
+ uint64_t &Target, int ArchRegWidth) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index a4e1d68beb534..664f95ddd8510 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -247,15 +247,13 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target) const override {
+ uint64_t &Target, int ArchRegWidth) const override {
switch(Inst.getOpcode()) {
default:
return false;
case RISCV::ADDI: {
if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- // TODO: Figure out ways to find the actual value of XLEN during analysis
- int XLEN = 32;
- uint64_t Mask = ~((uint64_t)0) >> (64 - XLEN);
+ uint64_t Mask = ~((uint64_t)0) >> (64 - ArchRegWidth);
Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
Target &= Mask;
return true;
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 871efe62f9de2..b45eb70312abd 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2323,8 +2323,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
+ int TargetArchBitWidth = DT->SubtargetInfo->getTargetTriple().getArchPointerBitWidth();
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target);
+ DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetArchBitWidth);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2353,27 +2354,37 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
// N.B. Except for XCOFF, we don't walk the relocations in the
// relocatable case yet.
std::vector<const SectionSymbolsTy *> TargetSectionSymbols;
+ bool AbsoluteFirst = false;
if (!Obj.isRelocatableObject()) {
auto It = llvm::partition_point(
SectionAddresses,
[=](const std::pair<uint64_t, SectionRef> &O) {
return O.first <= Target;
});
- uint64_t TargetSecAddr = 0;
+ uint64_t TargetSecAddr = It == SectionAddresses.end() ? It->first : 0;
+ bool FoundSymbols = false;
+ // missing case where begin == end as in this case, we are to return 0
while (It != SectionAddresses.begin()) {
--It;
- if (TargetSecAddr == 0)
- TargetSecAddr = It->first;
- if (It->first != TargetSecAddr)
- break;
+ if (It->first != TargetSecAddr) {
+ if (FoundSymbols)
+ break;
+ else {
+ TargetSecAddr = It->first;
+ AbsoluteFirst = true;
+ }
+ }
TargetSectionSymbols.push_back(&AllSymbols[It->second]);
- if (AllSymbols[It->second].empty())
- TargetSecAddr = 0;
+ if (!AllSymbols[It->second].empty())
+ FoundSymbols = true;
}
} else {
TargetSectionSymbols.push_back(&Symbols);
}
- TargetSectionSymbols.push_back(&AbsoluteSymbols);
+ if (AbsoluteFirst)
+ TargetSectionSymbols.insert(TargetSectionSymbols.begin(), &AbsoluteSymbols);
+ else
+ TargetSectionSymbols.push_back(&AbsoluteSymbols);
// Find the last symbol in the first candidate section whose
// offset is less than or equal to the target. If there are no
>From e425a7c59d83e741fb8f79d82b2f2c1933a72d24 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Thu, 21 Nov 2024 12:09:29 -0500
Subject: [PATCH 11/32] address comments, merge instruction evaluation and pass
register width through constructor
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 +-
llvm/lib/MC/MCInstrAnalysis.cpp | 2 +-
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 193 ++++++++----------
llvm/tools/llvm-objdump/llvm-objdump.cpp | 8 +-
4 files changed, 86 insertions(+), 120 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 1c32d4177effb..8e9418da395ac 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -14,6 +14,7 @@
#ifndef LLVM_MC_MCINSTRANALYSIS_H
#define LLVM_MC_MCINSTRANALYSIS_H
+#include "TargetRegistry.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
@@ -185,7 +186,7 @@ class MCInstrAnalysis {
/// the target address. Return true success, and the address in Target.
virtual bool
evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, int ArchRegWidth) const;
+ uint64_t &Target, raw_ostream *TargetOS) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 41a55637527da..92590c6d03f94 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -32,7 +32,7 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
uint64_t Addr, uint64_t Size,
- uint64_t &Target, int ArchRegWidth) const {
+ uint64_t &Target, raw_ostream *TargetOS) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 664f95ddd8510..860358e3a268c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -127,6 +127,7 @@ namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
int64_t GPRState[31] = {};
std::bitset<31> GPRValidMask;
+ int ArchRegWidth;
static bool isGPR(MCRegister Reg) {
return Reg >= RISCV::X0 && Reg <= RISCV::X31;
@@ -163,8 +164,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
- : MCInstrAnalysis(Info) {}
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, int ArchRegWidth)
+ : MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
void resetState() override { GPRValidMask.reset(); }
@@ -180,35 +181,28 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
switch (Inst.getOpcode()) {
- case RISCV::LUI: {
- setGPRState(Inst.getOperand(0).getReg(),
- SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
- break;
- }
- case RISCV::C_LUI: {
- MCRegister Reg = Inst.getOperand(0).getReg();
- if (Reg == RISCV::X2)
- break;
- setGPRState(Reg, SignExtend64<18>(Inst.getOperand(1).getImm() << 12));
- break;
-
- }
- case RISCV::AUIPC: {
- setGPRState(Inst.getOperand(0).getReg(),
- Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
- break;
- }
- default: {
- // Clear the state of all defined registers for instructions that we don't
- // explicitly support.
- auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
- for (unsigned I = 0; I < NumDefs; ++I) {
- auto DefReg = Inst.getOperand(I).getReg();
- if (isGPR(DefReg))
- setGPRState(DefReg, std::nullopt);
- }
- break;
+ case RISCV::C_LUI:
+ case RISCV::LUI: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ case RISCV::AUIPC: {
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+ break;
+ }
+ default: {
+ // Clear the state of all defined registers for instructions that we don't
+ // explicitly support.
+ auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
+ for (unsigned I = 0; I < NumDefs; ++I) {
+ auto DefReg = Inst.getOperand(I).getReg();
+ if (isGPR(DefReg))
+ setGPRState(DefReg, std::nullopt);
}
+ break;
+ }
}
}
@@ -247,90 +241,59 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, int ArchRegWidth) const override {
+ uint64_t &Target, raw_ostream *TargetOS) const override {
switch(Inst.getOpcode()) {
- default:
- return false;
- case RISCV::ADDI: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- uint64_t Mask = ~((uint64_t)0) >> (64 - ArchRegWidth);
- Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
- Target &= Mask;
- return true;
- }
- break;
- }
- case RISCV::ADDIW: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- uint64_t Mask = ~((uint64_t)0) >> 32;
- Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
- Target &= Mask;
- Target = SignExtend64<32>(Target);
- return true;
- }
- break;
- }
- case RISCV::C_ADDI: {
- int64_t Offset = Inst.getOperand(2).getImm();
- if (Offset == 0)
- break;
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- Target = *TargetRegState + SignExtend64<6>(Offset);
- return true;
- }
- break;
- }
- case RISCV::C_ADDIW: {
- int64_t Offset = Inst.getOperand(2).getImm();
- if (Offset == 0)
- break;
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- uint64_t Mask = ~((uint64_t)0) >> 32;
- Target &= Mask;
- Target = *TargetRegState + SignExtend64<6>(Offset);
- Target = SignExtend64<32>(Target);
- return true;
- }
- break;
+ default:
+ return false;
+ case RISCV::C_ADDI:
+ case RISCV::ADDI: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target &= maskTrailingOnes<uint64_t>(ArchRegWidth);
+ return true;
}
- case RISCV::LB:
- case RISCV::LH:
- case RISCV::LD:
- case RISCV::LW:
- case RISCV::LBU:
- case RISCV::LHU:
- case RISCV::LWU:
- case RISCV::SB:
- case RISCV::SH:
- case RISCV::SW:
- case RISCV::SD:
- case RISCV::FLH:
- case RISCV::FLW:
- case RISCV::FLD:
- case RISCV::FSH:
- case RISCV::FSW:
- case RISCV::FSD: {
- int64_t Offset = SignExtend64<12>(Inst.getOperand(2).getImm());
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
- Target = *TargetRegState + Offset;
- else
- Target = Offset;
+ break;
+ }
+ case RISCV::C_ADDIW:
+ case RISCV::ADDIW: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ Target = SignExtend64<32>(Target);
return true;
}
- case RISCV::C_LD:
- case RISCV::C_SD:
- case RISCV::C_FLD:
- case RISCV::C_FSD:
- case RISCV::C_SW:
- case RISCV::C_LW:
- case RISCV::C_FSW:
- case RISCV::C_FLW: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
- Target = *TargetRegState + Inst.getOperand(2).getImm();
- return true;
- }
- break;
+ break;
+ }
+ case RISCV::LB:
+ case RISCV::LH:
+ case RISCV::LD:
+ case RISCV::LW:
+ case RISCV::LBU:
+ case RISCV::LHU:
+ case RISCV::LWU:
+ case RISCV::SB:
+ case RISCV::SH:
+ case RISCV::SW:
+ case RISCV::SD:
+ case RISCV::FLH:
+ case RISCV::FLW:
+ case RISCV::FLD:
+ case RISCV::FSH:
+ case RISCV::FSW:
+ case RISCV::FSD:
+ case RISCV::C_LD:
+ case RISCV::C_SD:
+ case RISCV::C_FLD:
+ case RISCV::C_FSD:
+ case RISCV::C_SW:
+ case RISCV::C_LW:
+ case RISCV::C_FSW:
+ case RISCV::C_FLW: {
+ if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ Target = *TargetRegState + Inst.getOperand(2).getImm();
+ return true;
}
+ break;
+ }
}
return false;
}
@@ -428,8 +391,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
} // end anonymous namespace
-static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
- return new RISCVMCInstrAnalysis(Info);
+static MCInstrAnalysis *createRISCV32InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 32);
+}
+
+static MCInstrAnalysis *createRISCV64InstrAnalysis(const MCInstrInfo *Info) {
+ return new RISCVMCInstrAnalysis(Info, 64);
}
namespace {
@@ -455,12 +422,12 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
TargetRegistry::RegisterObjectTargetStreamer(
*T, createRISCVObjectTargetStreamer);
- TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
-
// Register the asm target streamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
// Register the null target streamer.
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
}
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(), createRISCV32InstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(), createRISCV64InstrAnalysis);
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index b45eb70312abd..5a48a654772d3 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2323,9 +2323,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- int TargetArchBitWidth = DT->SubtargetInfo->getTargetTriple().getArchPointerBitWidth();
bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetArchBitWidth);
+ DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetOS);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2361,9 +2360,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
[=](const std::pair<uint64_t, SectionRef> &O) {
return O.first <= Target;
});
- uint64_t TargetSecAddr = It == SectionAddresses.end() ? It->first : 0;
+ uint64_t TargetSecAddr = It == SectionAddresses.end() ? 0 : It->first;
bool FoundSymbols = false;
- // missing case where begin == end as in this case, we are to return 0
while (It != SectionAddresses.begin()) {
--It;
if (It->first != TargetSecAddr) {
@@ -2491,7 +2489,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
<< ">";
} else if (LabelAvailable) {
*TargetOS << " <" << AllLabels[Target] << ">";
- }
+ }
// By convention, each record in the comment stream should be
// terminated.
if (TargetOS == &CommentStream)
>From 571f056fa70dfcba6ab486fe14dd543cba3581fa Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Thu, 21 Nov 2024 12:19:00 -0500
Subject: [PATCH 12/32] remove debugging code
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 6 +++---
llvm/lib/MC/MCInstrAnalysis.cpp | 6 +++---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 9 ++++++---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 7 +++++--
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 8e9418da395ac..fb893d8e2f4eb 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -184,9 +184,9 @@ class MCInstrAnalysis {
/// Given an instruction that accesses a menory address, try to compute
/// the target address. Return true success, and the address in Target.
- virtual bool
- evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, raw_ostream *TargetOS) const;
+ virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size, uint64_t &Target,
+ raw_ostream *TargetOS) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 92590c6d03f94..c685883df9acc 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -30,9 +30,9 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
return false;
}
-bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
- uint64_t Addr, uint64_t Size,
- uint64_t &Target, raw_ostream *TargetOS) const {
+bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+ uint64_t Size, uint64_t &Target,
+ raw_ostream *TargetOS) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 860358e3a268c..125f8920461c1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -241,7 +241,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target, raw_ostream *TargetOS) const override {
+ uint64_t &Target,
+ raw_ostream *TargetOS) const override {
switch(Inst.getOpcode()) {
default:
return false;
@@ -428,6 +429,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
TargetRegistry::RegisterNullTargetStreamer(*T,
createRISCVNullTargetStreamer);
}
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(), createRISCV32InstrAnalysis);
- TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(), createRISCV64InstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV32Target(),
+ createRISCV32InstrAnalysis);
+ TargetRegistry::RegisterMCInstrAnalysis(getTheRISCV64Target(),
+ createRISCV64InstrAnalysis);
}
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 5a48a654772d3..938b753c134dd 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2323,8 +2323,11 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetOS);
+ bool PrintTarget =
+ DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index,
+ Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(
+ Inst, SectionAddr + Index, Size, Target, TargetOS);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From c36f94e5cd5980ff4f5066cadf47a5509300c856 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Thu, 21 Nov 2024 12:20:32 -0500
Subject: [PATCH 13/32] silly me forgot to save changes
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 4 ++--
llvm/lib/MC/MCInstrAnalysis.cpp | 4 ++--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 4 ++--
llvm/tools/llvm-objdump/llvm-objdump.cpp | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index fb893d8e2f4eb..4c2fa21ae7b56 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -185,8 +185,8 @@ class MCInstrAnalysis {
/// Given an instruction that accesses a menory address, try to compute
/// the target address. Return true success, and the address in Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target,
- raw_ostream *TargetOS) const;
+ uint64_t Size, uint64_t &Target
+ ) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index c685883df9acc..ac2df082c5112 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -31,8 +31,8 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
}
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target,
- raw_ostream *TargetOS) const {
+ uint64_t Size, uint64_t &Target
+ ) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 125f8920461c1..5541ac72e75fa 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -241,8 +241,8 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target,
- raw_ostream *TargetOS) const override {
+ uint64_t &Target
+ ) const override {
switch(Inst.getOpcode()) {
default:
return false;
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 938b753c134dd..6960d3855471f 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2327,7 +2327,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index,
Size, Target) ||
DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target, TargetOS);
+ Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From c461809b9ad4b21fb03121c5b15c6e39e12c4302 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Thu, 21 Nov 2024 12:21:32 -0500
Subject: [PATCH 14/32] run clang format
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 3 +--
llvm/lib/MC/MCInstrAnalysis.cpp | 4 ++--
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 3 +--
llvm/tools/llvm-objdump/llvm-objdump.cpp | 9 ++++-----
4 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 4c2fa21ae7b56..645b83f72795f 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -185,8 +185,7 @@ class MCInstrAnalysis {
/// Given an instruction that accesses a menory address, try to compute
/// the target address. Return true success, and the address in Target.
virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target
- ) const;
+ uint64_t Size, uint64_t &Target) const;
/// Given an instruction tries to get the address of a memory operand. Returns
/// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index ac2df082c5112..1ae0c91a2590c 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -31,8 +31,8 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
}
bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
- uint64_t Size, uint64_t &Target
- ) const {
+ uint64_t Size,
+ uint64_t &Target) const {
return false;
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 5541ac72e75fa..8f170ad484c5e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -241,8 +241,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
- uint64_t &Target
- ) const override {
+ uint64_t &Target) const override {
switch(Inst.getOpcode()) {
default:
return false;
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 6960d3855471f..3d87ec6af671b 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2323,11 +2323,10 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (Disassembled && DT->InstrAnalysis) {
llvm::raw_ostream *TargetOS = &FOS;
uint64_t Target;
- bool PrintTarget =
- DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index,
- Size, Target) ||
- DT->InstrAnalysis->evaluateInstruction(
- Inst, SectionAddr + Index, Size, Target);
+ bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
+ Inst, SectionAddr + Index, Size, Target) ||
+ DT->InstrAnalysis->evaluateInstruction(
+ Inst, SectionAddr + Index, Size, Target);
if (!PrintTarget) {
if (std::optional<uint64_t> MaybeTarget =
DT->InstrAnalysis->evaluateMemoryOperandAddress(
>From 96dd3c38de55242fe0eb94f846ffbce22b81b0b6 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 23 Dec 2024 16:25:35 -0500
Subject: [PATCH 15/32] fix code suggestion
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 3d87ec6af671b..71b9545f08b48 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2367,11 +2367,11 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
while (It != SectionAddresses.begin()) {
--It;
if (It->first != TargetSecAddr) {
- if (FoundSymbols)
- break;
- else {
+ if (!FoundSymbols) {
TargetSecAddr = It->first;
AbsoluteFirst = true;
+ } else {
+ break;
}
}
TargetSectionSymbols.push_back(&AllSymbols[It->second]);
>From 846d05555c13640425122d458695a4c7c6922239 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 23 Dec 2024 17:43:27 -0500
Subject: [PATCH 16/32] remove absolute first
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 71b9545f08b48..481324a8f5e1b 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2355,7 +2355,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
// N.B. Except for XCOFF, we don't walk the relocations in the
// relocatable case yet.
std::vector<const SectionSymbolsTy *> TargetSectionSymbols;
- bool AbsoluteFirst = false;
if (!Obj.isRelocatableObject()) {
auto It = llvm::partition_point(
SectionAddresses,
@@ -2369,7 +2368,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (It->first != TargetSecAddr) {
if (!FoundSymbols) {
TargetSecAddr = It->first;
- AbsoluteFirst = true;
} else {
break;
}
@@ -2381,10 +2379,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
} else {
TargetSectionSymbols.push_back(&Symbols);
}
- if (AbsoluteFirst)
- TargetSectionSymbols.insert(TargetSectionSymbols.begin(), &AbsoluteSymbols);
- else
- TargetSectionSymbols.push_back(&AbsoluteSymbols);
+ TargetSectionSymbols.push_back(&AbsoluteSymbols);
// Find the last symbol in the first candidate section whose
// offset is less than or equal to the target. If there are no
>From b78131200f77913fa9cd4c982e39d24274e8ccee Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Wed, 8 Jan 2025 16:06:06 -0500
Subject: [PATCH 17/32] objdump prioritize actual symbols over dummy symbols
during resolution
---
.../llvm/MC/MCDisassembler/MCDisassembler.h | 2 +
.../X86/disassemble-same-section-addr.test | 58 +++++++++++++++----
.../elf-disassemble-symbol-references.yaml | 4 +-
.../X86/section-filter-relocs.test | 2 +-
llvm/tools/llvm-objdump/llvm-objdump.cpp | 31 +++++++---
5 files changed, 76 insertions(+), 21 deletions(-)
diff --git a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
index 901bfcf5fa54f..eea405bb50f2e 100644
--- a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
+++ b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
@@ -34,12 +34,14 @@ struct SymbolInfoTy {
uint8_t Type;
// Used by ELF to describe a mapping symbol that is usually not displayed.
bool IsMappingSymbol;
+ bool IsDummy = false;
private:
bool IsXCOFF;
bool HasType;
public:
+ SymbolInfoTy() = default;
SymbolInfoTy(std::optional<XCOFF::StorageMappingClass> Smc, uint64_t Addr,
StringRef Name, std::optional<uint32_t> Idx, bool Label)
: Addr(Addr), Name(Name), XCOFFSymInfo{Smc, Idx, Label}, Type(0),
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
index 4b0da011c9d46..aa288e3ddf737 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
@@ -5,33 +5,33 @@
## to reproduce the original failure.
## Two empty sections, one with symbol in, one without.
-# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t1 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefix=TARGET
## Two sections, one empty with symbol, other non-empty, without symbol.
-# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=TARGET
-## Fall back to absolute symbol if no symbol found in candidate sections.
-# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS
+## Fall back to absolute symbols before dummy symbols if no symbols in candidate sections.
+# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS -D VALUE=0x6
# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=ABSOLUTE
## Show that other symbols with reserved st_shndx values are treated as absolute
-## symbols.
-# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC
+# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC -D VALUE=0x6
# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=ABSOLUTE
-## Print no target if no symbol in section/absolute symbol found.
+## Print dummy symbol if available and if no symbol in section/absolute symbol found.
# RUN: llvm-objcopy %t5 %t7 -N other
-# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
+# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=DUMMY
# TARGET: callq 0x5 <target>
# ABSOLUTE: callq 0x5 <other+0x5>
# FAIL: callq 0x5{{$}}
+# DUMMY: callq 0x5 <.caller+0x5>
--- !ELF
FileHeader:
@@ -58,7 +58,7 @@ Sections:
Symbols:
- Name: target
Section: [[SECTION]]
- Value: 0x5
+ Value: [[VALUE]]
- Name: other
Index: [[INDEX]]
Value: 0x0
@@ -112,3 +112,39 @@ Symbols:
- Name: second
Section: .second
Value: [[SYMVAL2]]
+
+## Fall back to symbols in earlier sections if no symbols in target section
+# RUN: yaml2obj %s --docnum=2 -o %t12 -D SIZE1=2 -D SIZE2=0 -D SYMVAL1=0x1 -D SYMVAL2=0x5 -D SYMSEC1=.caller
+# RUN: llvm-objdump -d %t12 | FileCheck %s --check-prefix=PREVSECSYM
+
+# PREVSECSYM: callq 0x5 <first+0x4>
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_X86_64
+Sections:
+ - Name: .caller
+ Type: SHT_PROGBITS
+ Flags: [SHF_ALLOC, SHF_EXECINSTR]
+ Address: 0x0
+ - Name: .first
+ Type: SHT_PROGBITS
+ Flags: [SHF_ALLOC, SHF_EXECINSTR]
+ Address: 0x3
+ Content: e800000000 ## Call instruction to next address.
+ Size: [[SIZE1]]
+ - Name: .second
+ Type: SHT_PROGBITS
+ Flags: [SHF_ALLOC, SHF_EXECINSTR]
+ Address: 0x5
+ Size: [[SIZE2]]
+Symbols:
+ - Name: first
+ Section: [[SYMSEC1]]
+ Value: [[SYMVAL1]]
+ - Name: second
+ Section: .second
+ Value: [[SYMVAL2]]
diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
index 973fd7dd5c2ff..20fb5adccfba0 100644
--- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
+++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
@@ -58,7 +58,7 @@ Symbols:
# REL: Disassembly of section .text1:
# REL-EMPTY:
# REL-NEXT: 0000000000000000 <.text1>:
-# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <.text1+0x5>
+# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <sym3+0x5>
# REL-EMPTY:
# REL-NEXT: Disassembly of section .text2:
# REL-EMPTY:
@@ -68,7 +68,7 @@ Symbols:
# REL-NEXT: Disassembly of section .text3:
# REL-EMPTY:
# REL-NEXT: 0000000000000000 <.text3>:
-# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <.text3+0x5>
+# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <sym3+0x5>
--- !ELF
FileHeader:
diff --git a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
index 002bd9349d163..ef8868462198a 100644
--- a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
+++ b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
@@ -10,7 +10,7 @@
# DISASM: Disassembly of section .text:
# DISASM-EMPTY:
# DISASM-NEXT: 0000000000000400 <.text>:
-# DISASM-NEXT: 400: e8 00 00 00 00 callq 0x405 <.text+0x5>
+# DISASM-NEXT: 400: e8 00 00 00 00 callq 0x405 <foo+0x405>
# RELOC-NEXT: 00000401: R_X86_64_PC32 foo+0x1
# RELOC-NEXT: 00000401: R_X86_64_GOT32 foo
# DISASM: Disassembly of section .rodata:
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 481324a8f5e1b..767288e23ebb7 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -61,6 +61,7 @@
#include "llvm/Object/MachOUniversal.h"
#include "llvm/Object/ObjectFile.h"
#include "llvm/Object/OffloadBinary.h"
+#include "llvm/Object/SymbolicFile.h"
#include "llvm/Object/Wasm.h"
#include "llvm/Option/Arg.h"
#include "llvm/Option/ArgList.h"
@@ -85,8 +86,10 @@
#include <cctype>
#include <cstring>
#include <optional>
+#include <queue>
#include <set>
#include <system_error>
+#include <unistd.h>
#include <unordered_map>
#include <utility>
@@ -1436,11 +1439,15 @@ SymbolInfoTy objdump::createSymbolInfo(const ObjectFile &Obj,
static SymbolInfoTy createDummySymbolInfo(const ObjectFile &Obj,
const uint64_t Addr, StringRef &Name,
uint8_t Type) {
+ SymbolInfoTy Ret;
if (Obj.isXCOFF() && (SymbolDescription || TracebackTable))
- return SymbolInfoTy(std::nullopt, Addr, Name, std::nullopt, false);
- if (Obj.isWasm())
- return SymbolInfoTy(Addr, Name, wasm::WASM_SYMBOL_TYPE_SECTION);
- return SymbolInfoTy(Addr, Name, Type);
+ Ret = SymbolInfoTy(std::nullopt, Addr, Name, std::nullopt, false);
+ else if (Obj.isWasm())
+ Ret = SymbolInfoTy(Addr, Name, wasm::WASM_SYMBOL_TYPE_SECTION);
+ else
+ Ret = SymbolInfoTy(Addr, Name, Type);
+ Ret.IsDummy = true;
+ return Ret;
}
static void collectBBAddrMapLabels(
@@ -2366,11 +2373,10 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
while (It != SectionAddresses.begin()) {
--It;
if (It->first != TargetSecAddr) {
- if (!FoundSymbols) {
+ if (!FoundSymbols)
TargetSecAddr = It->first;
- } else {
+ else
break;
- }
}
TargetSectionSymbols.push_back(&AllSymbols[It->second]);
if (!AllSymbols[It->second].empty())
@@ -2387,6 +2393,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
// using the nearest preceding absolute symbol (if any), if there
// are no other valid symbols.
const SymbolInfoTy *TargetSym = nullptr;
+ std::queue<const SymbolInfoTy *> DummySymbols;
for (const SectionSymbolsTy *TargetSymbols :
TargetSectionSymbols) {
auto It = llvm::partition_point(
@@ -2394,6 +2401,10 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
[=](const SymbolInfoTy &O) { return O.Addr <= Target; });
while (It != TargetSymbols->begin()) {
--It;
+ if (It->IsDummy) {
+ DummySymbols.push(&(*It));
+ continue;
+ }
// Skip mapping symbols to avoid possible ambiguity as they
// do not allow uniquely identifying the target address.
if (!It->IsMappingSymbol) {
@@ -2404,6 +2415,12 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (TargetSym)
break;
}
+ while (!DummySymbols.empty() && !TargetSym) {
+ const SymbolInfoTy *Sym = DummySymbols.front();
+ if (!Sym->IsMappingSymbol)
+ TargetSym = Sym;
+ DummySymbols.pop();
+ }
// Branch and instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
>From 146043d29af0222435ad376ac8c9b5e6485cc9f0 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Wed, 8 Jan 2025 17:33:17 -0500
Subject: [PATCH 18/32] remove unist.h from includes
---
llvm/tools/llvm-objdump/llvm-objdump.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 767288e23ebb7..d50a4248e5a69 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -89,7 +89,6 @@
#include <queue>
#include <set>
#include <system_error>
-#include <unistd.h>
#include <unordered_map>
#include <utility>
>From e8ea3bbe607e8fbde2838af35ed47058164bf41b Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 21 Jan 2025 17:06:08 -0500
Subject: [PATCH 19/32] Revert "objdump prioritize actual symbols over dummy
symbols during resolution"
This reverts commit b78131200f77913fa9cd4c982e39d24274e8ccee.
---
.../llvm/MC/MCDisassembler/MCDisassembler.h | 2 -
.../X86/disassemble-same-section-addr.test | 58 ++++---------------
.../elf-disassemble-symbol-references.yaml | 4 +-
.../X86/section-filter-relocs.test | 2 +-
llvm/tools/llvm-objdump/llvm-objdump.cpp | 30 +++-------
5 files changed, 21 insertions(+), 75 deletions(-)
diff --git a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
index eea405bb50f2e..901bfcf5fa54f 100644
--- a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
+++ b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
@@ -34,14 +34,12 @@ struct SymbolInfoTy {
uint8_t Type;
// Used by ELF to describe a mapping symbol that is usually not displayed.
bool IsMappingSymbol;
- bool IsDummy = false;
private:
bool IsXCOFF;
bool HasType;
public:
- SymbolInfoTy() = default;
SymbolInfoTy(std::optional<XCOFF::StorageMappingClass> Smc, uint64_t Addr,
StringRef Name, std::optional<uint32_t> Idx, bool Label)
: Addr(Addr), Name(Name), XCOFFSymInfo{Smc, Idx, Label}, Type(0),
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
index aa288e3ddf737..4b0da011c9d46 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
@@ -5,33 +5,33 @@
## to reproduce the original failure.
## Two empty sections, one with symbol in, one without.
-# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
+# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
# RUN: llvm-objdump -d %t1 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
+# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS
# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefix=TARGET
## Two sections, one empty with symbol, other non-empty, without symbol.
-# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
+# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
# RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
+# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=TARGET
-## Fall back to absolute symbols before dummy symbols if no symbols in candidate sections.
-# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS -D VALUE=0x6
+## Fall back to absolute symbol if no symbol found in candidate sections.
+# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS
# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=ABSOLUTE
## Show that other symbols with reserved st_shndx values are treated as absolute
-# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC -D VALUE=0x6
+## symbols.
+# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC
# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=ABSOLUTE
-## Print dummy symbol if available and if no symbol in section/absolute symbol found.
+## Print no target if no symbol in section/absolute symbol found.
# RUN: llvm-objcopy %t5 %t7 -N other
-# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=DUMMY
+# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
# TARGET: callq 0x5 <target>
# ABSOLUTE: callq 0x5 <other+0x5>
# FAIL: callq 0x5{{$}}
-# DUMMY: callq 0x5 <.caller+0x5>
--- !ELF
FileHeader:
@@ -58,7 +58,7 @@ Sections:
Symbols:
- Name: target
Section: [[SECTION]]
- Value: [[VALUE]]
+ Value: 0x5
- Name: other
Index: [[INDEX]]
Value: 0x0
@@ -112,39 +112,3 @@ Symbols:
- Name: second
Section: .second
Value: [[SYMVAL2]]
-
-## Fall back to symbols in earlier sections if no symbols in target section
-# RUN: yaml2obj %s --docnum=2 -o %t12 -D SIZE1=2 -D SIZE2=0 -D SYMVAL1=0x1 -D SYMVAL2=0x5 -D SYMSEC1=.caller
-# RUN: llvm-objdump -d %t12 | FileCheck %s --check-prefix=PREVSECSYM
-
-# PREVSECSYM: callq 0x5 <first+0x4>
-
---- !ELF
-FileHeader:
- Class: ELFCLASS64
- Data: ELFDATA2LSB
- Type: ET_EXEC
- Machine: EM_X86_64
-Sections:
- - Name: .caller
- Type: SHT_PROGBITS
- Flags: [SHF_ALLOC, SHF_EXECINSTR]
- Address: 0x0
- - Name: .first
- Type: SHT_PROGBITS
- Flags: [SHF_ALLOC, SHF_EXECINSTR]
- Address: 0x3
- Content: e800000000 ## Call instruction to next address.
- Size: [[SIZE1]]
- - Name: .second
- Type: SHT_PROGBITS
- Flags: [SHF_ALLOC, SHF_EXECINSTR]
- Address: 0x5
- Size: [[SIZE2]]
-Symbols:
- - Name: first
- Section: [[SYMSEC1]]
- Value: [[SYMVAL1]]
- - Name: second
- Section: .second
- Value: [[SYMVAL2]]
diff --git a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
index 20fb5adccfba0..973fd7dd5c2ff 100644
--- a/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
+++ b/llvm/test/tools/llvm-objdump/X86/elf-disassemble-symbol-references.yaml
@@ -58,7 +58,7 @@ Symbols:
# REL: Disassembly of section .text1:
# REL-EMPTY:
# REL-NEXT: 0000000000000000 <.text1>:
-# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <sym3+0x5>
+# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <.text1+0x5>
# REL-EMPTY:
# REL-NEXT: Disassembly of section .text2:
# REL-EMPTY:
@@ -68,7 +68,7 @@ Symbols:
# REL-NEXT: Disassembly of section .text3:
# REL-EMPTY:
# REL-NEXT: 0000000000000000 <.text3>:
-# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <sym3+0x5>
+# REL-NEXT: 0: e8 00 00 00 00 callq 0x5 <.text3+0x5>
--- !ELF
FileHeader:
diff --git a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
index ef8868462198a..002bd9349d163 100644
--- a/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
+++ b/llvm/test/tools/llvm-objdump/X86/section-filter-relocs.test
@@ -10,7 +10,7 @@
# DISASM: Disassembly of section .text:
# DISASM-EMPTY:
# DISASM-NEXT: 0000000000000400 <.text>:
-# DISASM-NEXT: 400: e8 00 00 00 00 callq 0x405 <foo+0x405>
+# DISASM-NEXT: 400: e8 00 00 00 00 callq 0x405 <.text+0x5>
# RELOC-NEXT: 00000401: R_X86_64_PC32 foo+0x1
# RELOC-NEXT: 00000401: R_X86_64_GOT32 foo
# DISASM: Disassembly of section .rodata:
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index d50a4248e5a69..481324a8f5e1b 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -61,7 +61,6 @@
#include "llvm/Object/MachOUniversal.h"
#include "llvm/Object/ObjectFile.h"
#include "llvm/Object/OffloadBinary.h"
-#include "llvm/Object/SymbolicFile.h"
#include "llvm/Object/Wasm.h"
#include "llvm/Option/Arg.h"
#include "llvm/Option/ArgList.h"
@@ -86,7 +85,6 @@
#include <cctype>
#include <cstring>
#include <optional>
-#include <queue>
#include <set>
#include <system_error>
#include <unordered_map>
@@ -1438,15 +1436,11 @@ SymbolInfoTy objdump::createSymbolInfo(const ObjectFile &Obj,
static SymbolInfoTy createDummySymbolInfo(const ObjectFile &Obj,
const uint64_t Addr, StringRef &Name,
uint8_t Type) {
- SymbolInfoTy Ret;
if (Obj.isXCOFF() && (SymbolDescription || TracebackTable))
- Ret = SymbolInfoTy(std::nullopt, Addr, Name, std::nullopt, false);
- else if (Obj.isWasm())
- Ret = SymbolInfoTy(Addr, Name, wasm::WASM_SYMBOL_TYPE_SECTION);
- else
- Ret = SymbolInfoTy(Addr, Name, Type);
- Ret.IsDummy = true;
- return Ret;
+ return SymbolInfoTy(std::nullopt, Addr, Name, std::nullopt, false);
+ if (Obj.isWasm())
+ return SymbolInfoTy(Addr, Name, wasm::WASM_SYMBOL_TYPE_SECTION);
+ return SymbolInfoTy(Addr, Name, Type);
}
static void collectBBAddrMapLabels(
@@ -2372,10 +2366,11 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
while (It != SectionAddresses.begin()) {
--It;
if (It->first != TargetSecAddr) {
- if (!FoundSymbols)
+ if (!FoundSymbols) {
TargetSecAddr = It->first;
- else
+ } else {
break;
+ }
}
TargetSectionSymbols.push_back(&AllSymbols[It->second]);
if (!AllSymbols[It->second].empty())
@@ -2392,7 +2387,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
// using the nearest preceding absolute symbol (if any), if there
// are no other valid symbols.
const SymbolInfoTy *TargetSym = nullptr;
- std::queue<const SymbolInfoTy *> DummySymbols;
for (const SectionSymbolsTy *TargetSymbols :
TargetSectionSymbols) {
auto It = llvm::partition_point(
@@ -2400,10 +2394,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
[=](const SymbolInfoTy &O) { return O.Addr <= Target; });
while (It != TargetSymbols->begin()) {
--It;
- if (It->IsDummy) {
- DummySymbols.push(&(*It));
- continue;
- }
// Skip mapping symbols to avoid possible ambiguity as they
// do not allow uniquely identifying the target address.
if (!It->IsMappingSymbol) {
@@ -2414,12 +2404,6 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
if (TargetSym)
break;
}
- while (!DummySymbols.empty() && !TargetSym) {
- const SymbolInfoTy *Sym = DummySymbols.front();
- if (!Sym->IsMappingSymbol)
- TargetSym = Sym;
- DummySymbols.pop();
- }
// Branch and instruction targets are printed just after the instructions.
// Print the labels corresponding to the target if there's any.
>From 1a23c2c7e722b92ed117be85c97c7aa819c02a3e Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Thu, 23 Jan 2025 16:12:29 -0500
Subject: [PATCH 20/32] modify test to effectively test new functionailty
---
.../X86/disassemble-same-section-addr.test | 27 ++++++++++---------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
index 4b0da011c9d46..0e50dab402b5f 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
@@ -5,33 +5,34 @@
## to reproduce the original failure.
## Two empty sections, one with symbol in, one without.
-# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t1 -D SIZE1=0 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t1 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t2 -D SIZE1=0 -D SIZE2=0 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t2 | FileCheck %s --check-prefix=TARGET
## Two sections, one empty with symbol, other non-empty, without symbol.
-# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t3 -D SIZE1=1 -D SIZE2=0 -D SECTION=.second -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t3 | FileCheck %s --check-prefix=TARGET
-# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS
+# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=TARGET
-## Fall back to absolute symbol if no symbol found in candidate sections.
-# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS
-# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=ABSOLUTE
+## Fall back to section symbols (if generated) and then absolute symbols if no symbol found in candidate sections.
+# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS -D VALUE=0x6
+# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=SECT
## Show that other symbols with reserved st_shndx values are treated as absolute
## symbols.
-# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC
-# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=ABSOLUTE
+# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC -D VALUE=0x6
+# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=SECT
## Print no target if no symbol in section/absolute symbol found.
-# RUN: llvm-objcopy %t5 %t7 -N other
-# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
+# RUN: llvm-objcopy %p/../ELF/Inputs/call-absolute-symbol.elf-x86_64 %t7 -N foo
+# RUN llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
# TARGET: callq 0x5 <target>
# ABSOLUTE: callq 0x5 <other+0x5>
-# FAIL: callq 0x5{{$}}
+# SECT: callq 0x5 <.caller+0x5>
+# FAIL: callq 0x100{{$}}
--- !ELF
FileHeader:
@@ -58,7 +59,7 @@ Sections:
Symbols:
- Name: target
Section: [[SECTION]]
- Value: 0x5
+ Value: [[VALUE]]
- Name: other
Index: [[INDEX]]
Value: 0x0
>From 707a1ed6b17daaf604e262ea1ad1a3ee3a6beefc Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Sun, 26 Jan 2025 13:07:31 -0500
Subject: [PATCH 21/32] Update .gitignore
---
.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitignore b/.gitignore
index 0e7c6c7900133..730295213a5af 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,6 +28,7 @@
# Nested build directory
/build*
+/local-tests
#==============================================================================#
# Explicit files to ignore (only matches one).
>From e94080f76bd32db688378e8e2fd19b8abb1c5517 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Sun, 26 Jan 2025 13:27:58 -0500
Subject: [PATCH 22/32] Update tests to match new functionality
---
lld/test/ELF/aarch64-gnu-ifunc-plt.s | 4 ++--
lld/test/ELF/i386-feature-cet.s | 2 +-
lld/test/ELF/x86-64-feature-cet.s | 4 ++--
.../tools/llvm-objdump/X86/disassemble-same-section-addr.test | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/lld/test/ELF/aarch64-gnu-ifunc-plt.s b/lld/test/ELF/aarch64-gnu-ifunc-plt.s
index 065aa3b36281f..a3eeb2e82caea 100644
--- a/lld/test/ELF/aarch64-gnu-ifunc-plt.s
+++ b/lld/test/ELF/aarch64-gnu-ifunc-plt.s
@@ -53,8 +53,8 @@
// DISASM: <bar>:
// DISASM-NEXT: 2102dc: ret
// DISASM: <_start>:
-// DISASM-NEXT: 2102e0: bl 0x210330 <zed2+0x210330>
-// DISASM-NEXT: 2102e4: bl 0x210340 <zed2+0x210340>
+// DISASM-NEXT: 2102e0: bl 0x210330 <zed2 at plt+0x10>
+// DISASM-NEXT: 2102e4: bl 0x210340 <zed2 at plt+0x20>
// DISASM-NEXT: 2102e8: bl 0x210310 <bar2 at plt>
// DISASM-NEXT: 2102ec: bl 0x210320 <zed2 at plt>
// DISASM-EMPTY:
diff --git a/lld/test/ELF/i386-feature-cet.s b/lld/test/ELF/i386-feature-cet.s
index d748a98e997c7..0db5dad5a5eef 100644
--- a/lld/test/ELF/i386-feature-cet.s
+++ b/lld/test/ELF/i386-feature-cet.s
@@ -58,7 +58,7 @@
# DISASM: Disassembly of section .text:
# DISASM: 00401200 <func1>:
-# DISASM-NEXT: 401200: calll 0x401230 <func2+0x401230>
+# DISASM-NEXT: 401200: calll 0x401230 <func1+0x30>
# DISASM-NEXT: 401205: calll 0x401240 <ifunc>
# DISASM-NEXT: retl
diff --git a/lld/test/ELF/x86-64-feature-cet.s b/lld/test/ELF/x86-64-feature-cet.s
index cf90d9708e119..509a7d6f55e1e 100644
--- a/lld/test/ELF/x86-64-feature-cet.s
+++ b/lld/test/ELF/x86-64-feature-cet.s
@@ -65,8 +65,8 @@
# DISASM: Disassembly of section .text:
# DISASM: 0000000000201330 <func1>:
-# DISASM-NEXT: 201330: callq 0x201360 <func2+0x201360>
-# DISASM-NEXT: 201335: callq 0x201370 <func2+0x201370>
+# DISASM-NEXT: 201330: callq 0x201360 <ifunc+0x25>
+# DISASM-NEXT: 201335: callq 0x201370 <ifunc+0x35>
# DISASM-NEXT: retq
# DISASM: Disassembly of section .plt:
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
index 0e50dab402b5f..ddc502568f622 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
@@ -27,7 +27,7 @@
## Print no target if no symbol in section/absolute symbol found.
# RUN: llvm-objcopy %p/../ELF/Inputs/call-absolute-symbol.elf-x86_64 %t7 -N foo
-# RUN llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
+# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
# TARGET: callq 0x5 <target>
# ABSOLUTE: callq 0x5 <other+0x5>
>From 4eb81b87e07a6c20e4b5211d9664f145527b9c68 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 18:35:53 -0400
Subject: [PATCH 23/32] Add tests of scenarios provided in issue description
(see issue related to pr)
---
.../tools/llvm-objdump/RISCV/Inputs/riscv-ar | Bin 0 -> 1062552 bytes
llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s | 57 ++++++++++++++++++
2 files changed, 57 insertions(+)
create mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar
new file mode 100755
index 0000000000000000000000000000000000000000..bc335bc24f88d8577308802b27dbded31834a89f
GIT binary patch
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HW3&Emjt;!3
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HcmV?d00001
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
new file mode 100644
index 0000000000000..49225519a62df
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar.s
@@ -0,0 +1,57 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar | FileCheck %s
+
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: ld a0, {{-?0x[0-9a-fA-F]+}}(a0) <ldata+0xfa4>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lw a0, {{-?0x[0-9a-fA-F]+}}(a0) <gdata>
+# CHECK: auipc a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}} <ldata>
+# CHECK: auipc ra, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jalr {{-?0x[0-9a-fA-F]+}}(ra) <func>
+# CHECK: auipc t1, {{-?0x[0-9a-fA-F]+}}
+# CHECK: jr {{-?0x[0-9a-fA-F]+}}(t1) <func>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x12242678>
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <gdata+0x1438ad>
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: slli a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addi a0, a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: lui a0, {{-?0x[0-9a-fA-F]+}}
+# CHECK: addiw a0, a0, {{-?0x[0-9a-fA-F]+}} <_start+0xfefff>
+
+.global _start
+.text
+_start:
+ la a0, gdata
+ lla a0, gdata
+ lla a0, gdata
+ lw a0, gdata
+ lla a0, ldata
+
+ call func
+ tail func
+
+ li a0, 0x12345678
+ li a0, 0x1234567890abcdef
+ li a0, 0x10000
+ li a0, 0xfffff
+
+ .skip 0x100000
+func:
+ ret
+
+ldata:
+ .int 0
+
+.data
+gdata:
+ .int 0
>From 4169bd4e3aa9e372979deea797afebc6b54726ba Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 18:38:19 -0400
Subject: [PATCH 24/32] Update tests to accurately match new symbol resolution
search pattern
---
.../X86/disassemble-same-section-addr.test | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
index ddc502568f622..ec10f76b12935 100644
--- a/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
+++ b/llvm/test/tools/llvm-objdump/X86/disassemble-same-section-addr.test
@@ -16,22 +16,16 @@
# RUN: yaml2obj %s --docnum=1 -o %t4 -D SIZE1=0 -D SIZE2=1 -D SECTION=.first -D INDEX=SHN_ABS -D VALUE=0x5
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=TARGET
-## Fall back to section symbols (if generated) and then absolute symbols if no symbol found in candidate sections.
-# RUN: yaml2obj %s --docnum=1 -o %t5 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_ABS -D VALUE=0x6
-# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=SECT
-
-## Show that other symbols with reserved st_shndx values are treated as absolute
-## symbols.
-# RUN: yaml2obj %s --docnum=1 -o %t6 -D SIZE1=1 -D SIZE2=0 -D SECTION=.caller -D INDEX=SHN_LOPROC -D VALUE=0x6
-# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=SECT
+## Fall back to absolute symbols if no symbol found in candidate sections.
+# RUN: llvm-objcopy -N foo --add-symbol absol=0 %p/../ELF/Inputs/call-absolute-symbol.elf-x86_64 %t5
+# RUN: llvm-objdump -d %t5 | FileCheck %s --check-prefix=ABSOLUTE
## Print no target if no symbol in section/absolute symbol found.
-# RUN: llvm-objcopy %p/../ELF/Inputs/call-absolute-symbol.elf-x86_64 %t7 -N foo
-# RUN: llvm-objdump -d %t7 | FileCheck %s --check-prefix=FAIL
+# RUN: llvm-objcopy %p/../ELF/Inputs/call-absolute-symbol.elf-x86_64 %t6 -N foo
+# RUN: llvm-objdump -d %t6 | FileCheck %s --check-prefix=FAIL
# TARGET: callq 0x5 <target>
-# ABSOLUTE: callq 0x5 <other+0x5>
-# SECT: callq 0x5 <.caller+0x5>
+# ABSOLUTE: callq 0x100 <absol+0x100>
# FAIL: callq 0x100{{$}}
--- !ELF
>From e52cbb903442719f56b746b387d18399a4bea0d5 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 18:38:59 -0400
Subject: [PATCH 25/32] Added tests to increase code coverage of new
functionality
---
.../RISCV/Inputs/riscv-ar-coverage | Bin 0 -> 1058192 bytes
.../llvm-objdump/RISCV/riscv-ar-coverage.s | 96 ++++++++++++++++++
2 files changed, 96 insertions(+)
create mode 100755 llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
new file mode 100755
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diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
new file mode 100644
index 0000000000000..98beb21a98354
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
@@ -0,0 +1,96 @@
+# RUN: llvm-objdump -d %p/Inputs/riscv-ar-coverage | FileCheck %s
+
+# CHECK: 0000000000001000 <_start>:
+# CHECK-NEXT: 1000: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 1004: 00450513 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 1008: 00001517 auipc a0, 0x1
+# CHECK-NEXT: 100c: 1571 addi a0, a0, -0x4 <target>
+# CHECK-NEXT: 100e: 6509 lui a0, 0x2
+# CHECK-NEXT: 1010: 0045059b addiw a1, a0, 0x4 <target>
+# CHECK-NEXT: 1014: 6509 lui a0, 0x2
+# CHECK-NEXT: 1016: 2511 addiw a0, a0, 0x4 <target>
+# CHECK-NEXT: 1018: 00102537 lui a0, 0x102
+# CHECK-NEXT: 101c: c50c sw a1, 0x8(a0) <far_target>
+# CHECK-NEXT: 101e: 00102537 lui a0, 0x102
+# CHECK-NEXT: 1022: 4508 lw a0, 0x8(a0) <far_target>
+# CHECK-NEXT: 1024: 6509 lui a0, 0x2
+# CHECK-NEXT: 1026: 6585 lui a1, 0x1
+# CHECK-NEXT: 1028: 0306 slli t1, t1, 0x1
+# CHECK-NEXT: 102a: 0511 addi a0, a0, 0x4 <target>
+# CHECK-NEXT: 102c: 0505 addi a0, a0, 0x1
+# CHECK-NEXT: 102e: 00200037 lui zero, 0x200
+# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
+# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
+# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
+
+.global _start
+.text
+
+# The core of the feature being added was address resolution for instruction
+# sequences where an register is populated by immediate values via two
+# separate instructions. First by an instruction that provides the upper bits
+# (auipc, lui ...) followed by another instruction for the lower bits (addi,
+# jalr, ld ...).
+
+
+_start:
+ # Test block 1-3 each focus on a certain starting instruction in a sequences,
+ # the ones that provide the upper bits. The other sequence is another
+ # instruction the provides the lower bits. The second instruction is
+ # arbitrarily chosen to increase code coverage
+
+ # test block #1
+ lla a0, target # addi
+
+ auipc a0, 0x1
+ c.addi a0, -0x4 # c.addi
+
+ # test block #2
+ c.lui a0, 0x2
+ addiw a1, a0, 0x4 # addiw
+
+ c.lui a0, 0x2
+ c.addiw a0, 0x4 # c.addiw
+
+ # test block #3
+ lui a0, 0x102
+ sw a1, 0x8(a0) # sw
+
+ lui a0, 0x102
+ c.lw a0, 0x8(a0) # lw
+
+ # Test block 4 tests instruction interleaving, essentially the code's
+ # ability to keep track of a valid sequence even if multiple other unrelated
+ # instructions separate the two
+
+ # test #4
+ lui a0, 0x2
+ lui a1, 0x1 # unrelated instruction
+ slli t1, t1, 0x1 # unrelated instruction
+ addi a0, a0, 0x4
+ addi a0, a0, 0x1
+
+ # Test 5 ensures that an instruction writing into the zero register does
+ # not trigger resolution because that register's value cannot change and
+ # the sequence is equivalent to never running the first instruction
+
+ # test #5
+ lui x0, 0x200
+ sw a0, 0x8(x0)
+
+ # Test 6 ensures that the newly added functionality is compatible with
+ # code that already worked for branch instructions
+
+ # test #6
+ call func
+
+# these are the labels that the instructions above are expecteed to resolve to
+.section .data
+.skip 0x4
+target:
+ .word 1
+.skip 0x100000
+far_target:
+ .word 2
+func:
+ ret
\ No newline at end of file
>From fe8424458d0098167ac28030154cffc84adf9894 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 18:39:11 -0400
Subject: [PATCH 26/32] Help llvm-lit find new tests
---
llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
diff --git a/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
new file mode 100644
index 0000000000000..17351748513d9
--- /dev/null
+++ b/llvm/test/tools/llvm-objdump/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "RISCV" in config.root.targets:
+ config.unsupported = True
>From f2b402bc8813be4fef50293aaf60e4e64bb5fde2 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 19:00:20 -0400
Subject: [PATCH 27/32] FIx zero register bug. Previously address resolution
would be triggered if the input register was the zero register.
---
.../Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 8f170ad484c5e..72bcf03d18875 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -247,7 +247,9 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
return false;
case RISCV::C_ADDI:
case RISCV::ADDI: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
Target = *TargetRegState + Inst.getOperand(2).getImm();
Target &= maskTrailingOnes<uint64_t>(ArchRegWidth);
return true;
@@ -256,7 +258,9 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
case RISCV::C_ADDIW:
case RISCV::ADDIW: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
Target = *TargetRegState + Inst.getOperand(2).getImm();
Target = SignExtend64<32>(Target);
return true;
@@ -288,7 +292,9 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::C_LW:
case RISCV::C_FSW:
case RISCV::C_FLW: {
- if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+ MCRegister Reg = Inst.getOperand(1).getReg();
+ auto TargetRegState = getGPRState(Reg);
+ if (TargetRegState && Reg != RISCV::X0) {
Target = *TargetRegState + Inst.getOperand(2).getImm();
return true;
}
>From 5f801eba1359cbb0154433fac778f203566d2944 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 19:06:04 -0400
Subject: [PATCH 28/32] Remove ignore of local folder as per comments
---
.gitignore | 1 -
1 file changed, 1 deletion(-)
diff --git a/.gitignore b/.gitignore
index 730295213a5af..0e7c6c7900133 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,7 +28,6 @@
# Nested build directory
/build*
-/local-tests
#==============================================================================#
# Explicit files to ignore (only matches one).
>From 7d66e20d601cd855fbb7c37b295697d247bcb017 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 19:12:09 -0400
Subject: [PATCH 29/32] Remove extraneous header as per comments
---
llvm/include/llvm/MC/MCInstrAnalysis.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 645b83f72795f..4886f74f36efb 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -14,7 +14,6 @@
#ifndef LLVM_MC_MCINSTRANALYSIS_H
#define LLVM_MC_MCINSTRANALYSIS_H
-#include "TargetRegistry.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
>From b42cdbb886e0d45c9f4521282cecfbee73125cc6 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Mon, 19 May 2025 19:13:59 -0400
Subject: [PATCH 30/32] Use unsigned instead of signed int for values that are
always positive - per comments
---
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 72bcf03d18875..bd553fee5d2b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -164,7 +164,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
}
public:
- explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, int ArchRegWidth)
+ explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info, unsigned int ArchRegWidth)
: MCInstrAnalysis(Info), ArchRegWidth(ArchRegWidth) {}
void resetState() override { GPRValidMask.reset(); }
>From 9476135d5538f0aa6743cdddeed1482402df1106 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Tue, 20 May 2025 19:03:02 -0400
Subject: [PATCH 31/32] Add support for Zcb extensions + corresponding tests
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 7 ++++++-
.../RISCV/Inputs/riscv-ar-coverage | Bin 1058192 -> 1058216 bytes
.../llvm-objdump/RISCV/riscv-ar-coverage.s | 15 ++++++++++++---
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index bd553fee5d2b5..dda4ab7a59ce0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -291,7 +291,12 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::C_SW:
case RISCV::C_LW:
case RISCV::C_FSW:
- case RISCV::C_FLW: {
+ case RISCV::C_FLW:
+ case RISCV::C_LBU:
+ case RISCV::C_LH:
+ case RISCV::C_LHU:
+ case RISCV::C_SB:
+ case RISCV::C_SH: {
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
if (TargetRegState && Reg != RISCV::X0) {
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
index 3359c887254d8a413f0cf49b5e6803f2e9611927..4e8a18f61a6a5836fc9136ad42718f3474a6a539 100755
GIT binary patch
delta 262
zcmbPm+F`|MhY1>t8WT0|bGk4<fXik<Mt(-lFeo={vL=%{hxMGJyRy%;JfFOfQDSoe
z(>Y!?a}@ywhK|jS0tfh~Hz)}RG%F~yD=07mF%u9o12GE_vjQ<25VHd at 2M}`tF&7YX
z12GQ}^8zv7b_E6g7yl=3VC0#mBEZ7m)ZiEjw7e*@IJu00(R;eIf`Fbxd{t&zYF=_`
zrcr at Gd{uIyA(%=sobIk5pbv5Y+x9vIfg)x`m+2ps1?m~YrWdLRm@}qKU#TKs&sZ`2
aC5XzHuBj?u&-p?T=yV{knO>+QAP)eR*G1R>
delta 227
zcmZ2++F=3^X)p>*)V$AW#{dC#n*|y9898mBT${<7OzIp9W49kXEY0IIc_E|3<^ra3
zyqg6Tj`2^Qpdi3DeV&p4SF?gbyMh8E5HkTWGZ3=?F)I+W0Wmuea{w_X5OV=BHxTmx
zF)tAFZC6m>fAN3v21XuXCZL^74UX18swlHKxr~9)aJsaDfZp_E1p(ddeF_3q%#3!^
uIaLJe8EvLFDhP;9pQj?A#OO8spo)M!W5RSsRUj2G-4R4xnBJ%=pbh{sW;mMw
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
index 98beb21a98354..ba437f356fbde 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
@@ -22,6 +22,8 @@
# CHECK-NEXT: 1032: 00a02423 sw a0, 0x8(zero)
# CHECK-NEXT: 1036: 00101097 auipc ra, 0x101
# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
+# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
+# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
.global _start
.text
@@ -41,21 +43,18 @@ _start:
# test block #1
lla a0, target # addi
-
auipc a0, 0x1
c.addi a0, -0x4 # c.addi
# test block #2
c.lui a0, 0x2
addiw a1, a0, 0x4 # addiw
-
c.lui a0, 0x2
c.addiw a0, 0x4 # c.addiw
# test block #3
lui a0, 0x102
sw a1, 0x8(a0) # sw
-
lui a0, 0x102
c.lw a0, 0x8(a0) # lw
@@ -84,6 +83,16 @@ _start:
# test #6
call func
+ # test #7 zcb extension
+ lui x8, 0x102
+ # the immediate value for Zcb extension is heavily bounded, so we will relax
+ # the requirement of hitting one of the labels and focus on correctness of the
+ # resolution. This can be verified by looking at the source: The upper bits of
+ # lui make the far jump related to .skip 0x100000 and then 8 more bytes must be
+ # traversed before we hit far_target--.skip 0x4 and .word 1 in target. Adding 8
+ # to address resolved for the instruction below yields exactly the desired label.
+ c.sb x8, 0(x8)
+
# these are the labels that the instructions above are expecteed to resolve to
.section .data
.skip 0x4
>From e3e96c5d99eac5be7b271666b82b40c14f380a77 Mon Sep 17 00:00:00 2001
From: arjunUpatel <arjunpatel151002 at gmail.com>
Date: Wed, 21 May 2025 00:02:47 -0400
Subject: [PATCH 32/32] Added support for stack pointer based load and stores
---
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 10 +++++++++-
.../RISCV/Inputs/riscv-ar-coverage | Bin 1058216 -> 1058216 bytes
.../llvm-objdump/RISCV/riscv-ar-coverage.s | 6 ++++++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index dda4ab7a59ce0..0624d498ed5a0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -296,7 +296,15 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
case RISCV::C_LH:
case RISCV::C_LHU:
case RISCV::C_SB:
- case RISCV::C_SH: {
+ case RISCV::C_SH:
+ case RISCV::C_LWSP:
+ case RISCV::C_SWSP:
+ case RISCV::C_LDSP:
+ case RISCV::C_SDSP:
+ case RISCV::C_FLWSP:
+ case RISCV::C_FSWSP:
+ case RISCV::C_FLDSP:
+ case RISCV::C_FSDSP: {
MCRegister Reg = Inst.getOperand(1).getReg();
auto TargetRegState = getGPRState(Reg);
if (TargetRegState && Reg != RISCV::X0) {
diff --git a/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage b/llvm/test/tools/llvm-objdump/RISCV/Inputs/riscv-ar-coverage
index 4e8a18f61a6a5836fc9136ad42718f3474a6a539..08ba4f884605001094c28ce355201e6842b8d08f 100755
GIT binary patch
delta 146
zcmZ2++F`|MhYcKzoL&qN;I&zh(VmgRjp5Jl7wdGCCNE@^*j&JLg_q4-QGh|ob+e$t
zF8=8g6a?6&&r=fMYF1EaS5ROCVkRJF24WT<W(8t4AZ7<*4j|?PVlE)&24Wr{<^^KD
c?FtI~FaA&7z{s<lLqULr(Q7-WiokqE08cz6n*aa+
delta 139
zcmZ2++F`|MhYcKzoGuIy;Idhe(VmgRdd|^Z*=JgwPhQ9<vAKZh3h!n?g#-N4CnyN8
zO`oSEz}2jv(5|4s2*gZ4%nZaVK+FonY(UHo#2i4(3B+7L%nigmK+FroeA^Wi_+R{=
Vyn&HtIfsG(3!}?+P8EUqi~#jeC6NFC
diff --git a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
index ba437f356fbde..4f915da0765be 100644
--- a/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
+++ b/llvm/test/tools/llvm-objdump/RISCV/riscv-ar-coverage.s
@@ -24,6 +24,8 @@
# CHECK-NEXT: 103a: fd6080e7 jalr -0x2a(ra) <func>
# CHECK-NEXT: 103e: 00102437 lui s0, 0x102
# CHECK-NEXT: 1042: 8800 sb s0, 0x0(s0) <target+0xffffc>
+# CHECK-NEXT: 1044: 00102137 lui sp, 0x102
+# CHECK-NEXT: 1048: 4522 lw a0, 0x8(sp) <far_target>
.global _start
.text
@@ -93,6 +95,10 @@ _start:
# to address resolved for the instruction below yields exactly the desired label.
c.sb x8, 0(x8)
+ # test #8 stack based load/stores
+ lui sp, 0x102
+ c.lwsp a0, 0x8(sp)
+
# these are the labels that the instructions above are expecteed to resolve to
.section .data
.skip 0x4
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