[llvm] [WIP][AMDGPU][MC] Support 128b rsrc reg in mimg instructions (PR #139121)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue May 20 10:59:16 PDT 2025
https://github.com/jwanggit86 updated https://github.com/llvm/llvm-project/pull/139121
>From c9f698f4f42d20c454dff50157978d13c6e8f243 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 23 Apr 2025 11:56:22 -0700
Subject: [PATCH 1/9] [AMDGPU[MC] Allow 128-bit rsrc register in MIMG
instructions
The r128 field in MIMG instructions indicates that the resource register
is 128-bit. However, the assembler will reject instructions with 128-bit
resource register even when r128 is present. This patch fixes this problem.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 7 +
.../Disassembler/AMDGPUDisassembler.cpp | 1 +
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 4 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 9 +
.../GlobalISel/irtranslator-inline-asm.ll | 32 +-
.../AMDGPU/branch-relax-indirect-branch.mir | 4 +-
.../AMDGPU/branch-relax-no-terminators.mir | 4 +-
.../coalesce-copy-to-agpr-to-av-registers.mir | 92 ++---
.../AMDGPU/coalescer-early-clobber-subreg.mir | 16 +-
llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir | 4 +-
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll | 37 +-
...local-stack-alloc-add-references.gfx10.mir | 30 +-
.../local-stack-alloc-add-references.gfx8.mir | 360 +++++++++---------
.../local-stack-alloc-add-references.gfx9.mir | 180 ++++-----
...al-regcopy-and-spill-missed-at-regalloc.ll | 45 ++-
...ssert-dead-def-subreg-use-other-subreg.mir | 4 +-
...dleMoveUp-subreg-def-across-subreg-def.mir | 16 +-
.../CodeGen/AMDGPU/spill-vector-superclass.ll | 6 +-
...ubreg-undef-def-with-other-subreg-defs.mir | 24 +-
.../Inputs/amdgpu_isel.ll.expected | 20 +-
20 files changed, 455 insertions(+), 440 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 28370b8670f05..7467d58ffe5d2 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9786,6 +9786,13 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
case MCK_SReg_256:
case MCK_SReg_512:
return Operand.isNull() ? Match_Success : Match_InvalidOperand;
+ case MCK_SReg_RSRC: {
+ if (Operand.isReg())
+ if (Operand.isRegClass(SReg_128_XNULLRegClassID) ||
+ Operand.isRegClass(SReg_256_XNULLRegClassID))
+ return Match_Success;
+ return Match_InvalidOperand;
+ }
default:
return Match_InvalidOperand;
}
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index ca0093d1f049c..c0786252c4849 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -268,6 +268,7 @@ DECODE_OPERAND_SREG_7(SReg_128, 128)
DECODE_OPERAND_SREG_7(SReg_128_XNULL, 128)
DECODE_OPERAND_SREG_7(SReg_256, 256)
DECODE_OPERAND_SREG_7(SReg_256_XNULL, 256)
+DECODE_OPERAND_SREG_7(SReg_RSRC, 256)
DECODE_OPERAND_SREG_7(SReg_512, 512)
DECODE_OPERAND_SREG_8(SReg_64, 64)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 8d94d73bc1aab..91756b9fd6678 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -877,7 +877,7 @@ class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
let Constraints = "$vdst = $vdata";
- let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
+ let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_RSRC:$srsrc,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da";
@@ -923,7 +923,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
!if(enableDisasm, "GFX10", "")> {
let Constraints = "$vdst = $vdata";
- let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
+ let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index d595163f820cb..721f31a0c49d0 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -922,6 +922,15 @@ defm "" : SRegClass<16, Reg512Types.types, SGPR_512Regs, TTMP_512Regs>;
defm "" : SRegClass<32, Reg1024Types.types, SGPR_1024Regs>;
}
+def SReg_RSRC : SIRegisterClass<"AMDGPU", [v8i32], 32,
+ (add SReg_256_XNULL, SReg_128_XNULL)> {
+ let Size = 8;
+ let CopyCost = -1;
+ let isAllocatable = 0;
+ let HasSGPR = 1;
+ let BaseClassOrder = 10000;
+}
+
def VRegOrLds_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
(add VGPR_32, LDS_DIRECT_CLASS)> {
let isAllocatable = 0;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
index 96c9f40e317ea..cf2fd88405cec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
@@ -66,7 +66,7 @@ define amdgpu_kernel void @asm_simple_agpr_clobber() {
define i32 @asm_vgpr_early_clobber() {
; CHECK-LABEL: name: asm_vgpr_early_clobber
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 2228235 /* regdef-ec:VGPR_32 */, def early-clobber %8, 2228235 /* regdef-ec:VGPR_32 */, def early-clobber %9, !1
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 3211275 /* regdef-ec:VGPR_32 */, def early-clobber %8, 3211275 /* regdef-ec:VGPR_32 */, def early-clobber %9, !1
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
@@ -94,7 +94,7 @@ entry:
define i32 @test_single_vgpr_output() nounwind {
; CHECK-LABEL: name: test_single_vgpr_output
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 3211274 /* regdef:VGPR_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -106,7 +106,7 @@ entry:
define i32 @test_single_sgpr_output_s32() nounwind {
; CHECK-LABEL: name: test_single_sgpr_output_s32
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 2359306 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 3342346 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -119,7 +119,7 @@ entry:
define float @test_multiple_register_outputs_same() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_same
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %8, 2228234 /* regdef:VGPR_32 */, def %9
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 3211274 /* regdef:VGPR_32 */, def %8, 3211274 /* regdef:VGPR_32 */, def %9
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]
@@ -136,7 +136,7 @@ define float @test_multiple_register_outputs_same() #0 {
define double @test_multiple_register_outputs_mixed() #0 {
; CHECK-LABEL: name: test_multiple_register_outputs_mixed
; CHECK: bb.1 (%ir-block.0):
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %8, 3538954 /* regdef:VReg_64 */, def %9
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 3211274 /* regdef:VGPR_32 */, def %8, 4521994 /* regdef:VReg_64 */, def %9
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %9
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
@@ -171,7 +171,7 @@ define amdgpu_kernel void @test_input_vgpr_imm() {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[C]](s32)
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0
call void asm sideeffect "v_mov_b32 v0, $0", "v"(i32 42)
ret void
@@ -185,7 +185,7 @@ define amdgpu_kernel void @test_input_sgpr_imm() {
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[C]](s32)
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0
call void asm sideeffect "s_mov_b32 s0, $0", "s"(i32 42)
ret void
@@ -212,7 +212,7 @@ define float @test_input_vgpr(i32 %src) nounwind {
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
- ; CHECK-NEXT: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %9, 2228233 /* reguse:VGPR_32 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 3211274 /* regdef:VGPR_32 */, def %9, 3211273 /* reguse:VGPR_32 */, [[COPY1]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -227,7 +227,7 @@ define i32 @test_memory_constraint(ptr addrspace(3) %a) nounwind {
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 2228234 /* regdef:VGPR_32 */, def %9, 262158 /* mem:m */, [[COPY]](p3)
+ ; CHECK-NEXT: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 3211274 /* regdef:VGPR_32 */, def %9, 262158 /* mem:m */, [[COPY]](p3)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9
; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -244,7 +244,7 @@ define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AND]](s32)
- ; CHECK-NEXT: INLINEASM &";", 1 /* sideeffect attdialect */, 2228234 /* regdef:VGPR_32 */, def %11, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &";", 1 /* sideeffect attdialect */, 3211274 /* regdef:VGPR_32 */, def %11, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %11
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -256,13 +256,13 @@ define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {
define i32 @test_sgpr_matching_constraint() nounwind {
; CHECK-LABEL: name: test_sgpr_matching_constraint
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 2359306 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 3342346 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 2359306 /* regdef:SReg_32 */, def %10
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 3342346 /* regdef:SReg_32 */, def %10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %10
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 2359306 /* regdef:SReg_32 */, def %12, 2359305 /* reguse:SReg_32 */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 3342346 /* regdef:SReg_32 */, def %12, 3342345 /* reguse:SReg_32 */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY %12
; CHECK-NEXT: $vgpr0 = COPY [[COPY4]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
@@ -285,7 +285,7 @@ define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)
- ; CHECK-NEXT: INLINEASM &"; ", 1 /* sideeffect attdialect */, 2228234 /* regdef:VGPR_32 */, def %11, 2228234 /* regdef:VGPR_32 */, def %12, 2228234 /* regdef:VGPR_32 */, def %13, 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY4]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY5]](tied-def 5)
+ ; CHECK-NEXT: INLINEASM &"; ", 1 /* sideeffect attdialect */, 3211274 /* regdef:VGPR_32 */, def %11, 3211274 /* regdef:VGPR_32 */, def %12, 3211274 /* regdef:VGPR_32 */, def %13, 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY4]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY5]](tied-def 5)
; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY %11
; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY %12
; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY %13
@@ -306,10 +306,10 @@ define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {
define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {
; CHECK-LABEL: name: test_sgpr_to_vgpr_move_matching_constraint
; CHECK: bb.1.entry:
- ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 2359306 /* regdef:SReg_32 */, def %8
+ ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 3342346 /* regdef:SReg_32 */, def %8
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)
- ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 2228234 /* regdef:VGPR_32 */, def %10, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 3211274 /* regdef:VGPR_32 */, def %10, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %10
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
index 253e7e278aaff..b0c037837b935 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
@@ -68,7 +68,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.7(0x7c000000)
; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 2097162 /* regdef:VRegOrLds_32 */, def renamable $sgpr4
+ ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 3342346 /* regdef:SReg_32 */, def renamable $sgpr4
; CHECK-NEXT: S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
; CHECK-NEXT: S_CBRANCH_SCC0 %bb.3, implicit killed $scc
; CHECK-NEXT: {{ $}}
@@ -149,7 +149,7 @@ body: |
successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
- INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 2097162 /* regdef:SReg_32 */, def renamable $sgpr4
+ INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 3342346 /* regdef:SReg_32 */, def renamable $sgpr4
S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
S_CBRANCH_SCC1 %bb.2, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
index 474ba71b0ebac..855a710bf8d1e 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
+++ b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
@@ -69,7 +69,7 @@ body: |
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.7(0x7c000000)
; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 2097162 /* regdef:VRegOrLds_32 */, def renamable $sgpr4
+ ; CHECK-NEXT: INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 3342346 /* regdef:SReg_32 */, def renamable $sgpr4
; CHECK-NEXT: S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
; CHECK-NEXT: S_CBRANCH_SCC0 %bb.3, implicit killed $scc
; CHECK-NEXT: {{ $}}
@@ -151,7 +151,7 @@ body: |
successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1
- INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 2097162 /* regdef:SReg_32 */, def renamable $sgpr4
+ INLINEASM &"v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64\0A v_nop_e64", 1 /* sideeffect attdialect */, 3342346 /* regdef:SReg_32 */, def renamable $sgpr4
S_CMP_LG_U32 killed renamable $sgpr4, 0, implicit-def $scc
S_CBRANCH_SCC1 %bb.2, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
index f153b30c80b22..69c0463d7d430 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
@@ -20,13 +20,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -45,13 +45,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -72,7 +72,7 @@ body: |
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96 = COPY [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY3]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
@@ -80,7 +80,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0
%3.sub1:areg_96 = COPY %1
%3.sub2:areg_96 = COPY %2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -101,7 +101,7 @@ body: |
; CHECK-NEXT: undef [[COPY3:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY3]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
@@ -109,7 +109,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0
%3.sub1:areg_96_align2 = COPY %1
%3.sub2:areg_96_align2 = COPY %2
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -128,13 +128,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vreg_64 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0
%2.sub2_sub3:areg_128 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -153,13 +153,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vreg_64 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0
%2.sub2_sub3:areg_128_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -178,13 +178,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:sgpr_32 = COPY $sgpr8
%1:sgpr_32 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -203,13 +203,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0
%2.sub1_sub2:areg_96 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -228,13 +228,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0
%2.sub1_sub2:areg_96_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -253,13 +253,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0
%2.sub2:areg_96 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -278,13 +278,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%1:vgpr_32 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0
%2.sub2:areg_96_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -302,12 +302,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -326,13 +326,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0
%2.sub1:areg_64_align2 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -350,12 +350,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_96 = COPY %0
%1.sub1:areg_96 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %1
SI_RETURN
...
@@ -373,12 +373,12 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_96_align2 = COPY %0
%1.sub1:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %1
SI_RETURN
...
@@ -398,14 +398,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_128 = COPY %0
%1.sub1:areg_128 = COPY %0
%1.sub2:areg_128 = COPY %0
%1.sub3:areg_128 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %1
SI_RETURN
...
@@ -425,14 +425,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128_align2 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_128_align2 = COPY %0
%1.sub1:areg_128_align2 = COPY %0
%1.sub2:areg_128_align2 = COPY %0
%1.sub3:areg_128_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %1
SI_RETURN
...
@@ -451,15 +451,15 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1:areg_64 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY2]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0
%2.sub1:areg_64 = COPY %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
- INLINEASM &"; use $0", 0 /* attdialect */, 2228233 /* reguse:VGPR_32 */, killed %0
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 3211273 /* reguse:VGPR_32 */, killed %0
SI_RETURN
...
@@ -477,14 +477,14 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]]
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_64 = COPY %0
%1.sub1:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %1
- INLINEASM &"; use $0", 0 /* attdialect */, 2228233 /* reguse:VGPR_32 */, killed %0
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 3211273 /* reguse:VGPR_32 */, killed %0
SI_RETURN
...
@@ -503,16 +503,16 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3538953 /* reguse:VReg_64 */, [[COPY]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4521993 /* reguse:VReg_64 */, [[COPY]]
; CHECK-NEXT: SI_RETURN
%0:vgpr_32 = COPY $vgpr0
undef %1.sub0:areg_64 = COPY %0
%1.sub1:areg_64 = COPY %0
undef %2.sub0:vreg_64 = COPY %0
%2.sub1:vreg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %1
- INLINEASM &"; use $0", 0 /* attdialect */, 3538953 /* reguse:VReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 4521993 /* reguse:VReg_64 */, killed %2
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
index 4404f1aa37c5d..1777b6caf35dd 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
@@ -20,10 +20,10 @@ body: |
; CHECK-LABEL: name: foo1
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1835018 /* regdef:VS_32 */, def undef %2.sub0, 1835019 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 2818058 /* regdef:VS_32 */, def undef %2.sub0, 2818059 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %0:vgpr_32, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 2818058 /* regdef:VGPR_32 */, def %0:vgpr_32, 2818059 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %0
%2.sub1:vreg_64 = COPY killed %1
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -41,10 +41,10 @@ body: |
; CHECK-LABEL: name: foo2
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1835019 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1, 1835018 /* regdef:VS_32 */, def undef %2.sub0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 2818059 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1, 2818058 /* regdef:VS_32 */, def undef %2.sub0
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32, 1835018 /* regdef:VGPR_32 */, def %0:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 2818059 /* regdef-ec:VGPR_32 */, def early-clobber %1:vgpr_32, 2818058 /* regdef:VGPR_32 */, def %0:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %0
%2.sub1:vreg_64 = COPY killed %1
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -62,10 +62,10 @@ body: |
; CHECK-LABEL: name: foo3
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1835018 /* regdef:VS_32 */, def undef %2.sub0, 1835019 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 2818058 /* regdef:VS_32 */, def undef %2.sub0, 2818059 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1835018 /* regdef:VGPR_32 */, def %1:vgpr_32, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 2818058 /* regdef:VGPR_32 */, def %1:vgpr_32, 2818059 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %1
%2.sub1:vreg_64 = COPY killed %0
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
@@ -83,10 +83,10 @@ body: |
; CHECK-LABEL: name: foo4
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 1835019 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1, 1835018 /* regdef:VS_32 */, def undef %2.sub0
+ ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 2818059 /* regdef-ec:VS_32 */, def undef early-clobber %2.sub1, 2818058 /* regdef:VS_32 */, def undef %2.sub0
; CHECK-NEXT: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
; CHECK-NEXT: S_ENDPGM 0
- INLINEASM &"", 0 /* attdialect */, 1835019 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32, 1835018 /* regdef:VGPR_32 */, def %1:vgpr_32
+ INLINEASM &"", 0 /* attdialect */, 2818059 /* regdef-ec:VGPR_32 */, def early-clobber %0:vgpr_32, 2818058 /* regdef:VGPR_32 */, def %1:vgpr_32
undef %2.sub0:vreg_64 = COPY killed %1
%2.sub1:vreg_64 = COPY killed %0
FLAT_STORE_DWORDX2 killed $vgpr0_vgpr1, killed %2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64))
diff --git a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
index 49576433ab54d..aaf881ca3abac 100644
--- a/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
+++ b/llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
@@ -1112,11 +1112,11 @@ body: |
; GCN-NEXT: S_WAITCNT 0
; GCN-NEXT: renamable $vgpr2 = V_CVT_SCALEF32_PK_FP4_F16_e64 8, killed $vgpr0, 0, killed $vgpr1, 4, killed $vgpr2, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, killed renamable $vgpr2
+ ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, killed renamable $vgpr2
; GCN-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31
S_WAITCNT 0
renamable $vgpr2 = V_CVT_SCALEF32_PK_FP4_F16_e64 8, killed $vgpr0, 0, killed $vgpr1, 4, killed $vgpr2, 0, implicit $mode, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, killed renamable $vgpr2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, killed renamable $vgpr2
S_SETPC_B64_return undef $sgpr30_sgpr31
...
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
index 0ca180ed6e105..b15f9e5a33646 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
@@ -8,16 +8,16 @@
define amdgpu_kernel void @s_input_output_i128() {
; GFX908-LABEL: name: s_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7208970 /* regdef:SGPR_128 */, def %13
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7208969 /* reguse:SGPR_128 */, %14
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %12
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8192009 /* reguse:SGPR_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: s_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7208970 /* regdef:SGPR_128 */, def %11
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7208969 /* reguse:SGPR_128 */, %12
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %10
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8192009 /* reguse:SGPR_128 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=s"()
call void asm sideeffect "; use $0", "s"(i128 %val)
@@ -27,16 +27,16 @@ define amdgpu_kernel void @s_input_output_i128() {
define amdgpu_kernel void @v_input_output_i128() {
; GFX908-LABEL: name: v_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6094858 /* regdef:VReg_128 */, def %13
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6094857 /* reguse:VReg_128 */, %14
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %12
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7077897 /* reguse:VReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: v_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6422538 /* regdef:VReg_128_Align2 */, def %11
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6422537 /* reguse:VReg_128_Align2 */, %12
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %10
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:VReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=v"()
call void asm sideeffect "; use $0", "v"(i128 %val)
@@ -46,17 +46,16 @@ define amdgpu_kernel void @v_input_output_i128() {
define amdgpu_kernel void @a_input_output_i128() {
; GFX908-LABEL: name: a_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6029322 /* regdef:AReg_128 */, def %13
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %13
- ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6029321 /* reguse:AReg_128 */, %14
-
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:AReg_128 */, def %12
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: a_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6291466 /* regdef:AReg_128_Align2 */, def %11
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %11
- ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %12
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7274506 /* regdef:AReg_128_Align2 */, def %10
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = call i128 asm sideeffect "; def $0", "=a"()
call void asm sideeffect "; use $0", "a"(i128 %val)
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
index 0c31b36e90cb0..6b25be37279a1 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
@@ -18,21 +18,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], 256, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 256, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %stack.0, 512, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -53,27 +53,27 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], -156, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 256, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 512, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
%2:vgpr_32 = V_ADD_U32_e64 %stack.0, 100, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %2
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
index 6758db41506a7..39dcb06c591db 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
@@ -21,9 +21,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -31,9 +31,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -41,10 +41,10 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -52,9 +52,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
@@ -62,15 +62,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -88,42 +88,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX803: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX900: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX942: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX10: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets_live_vcc
; GFX12: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]], implicit $vcc
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 256, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 512, %stack.0, implicit-def $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1, implicit $vcc
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1, implicit $vcc
SI_RETURN
...
@@ -144,9 +144,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -154,9 +154,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -164,10 +164,10 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -175,9 +175,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
@@ -185,15 +185,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_CO_U32_e32 8, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 16, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -214,9 +214,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_CO_U32_e64_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -224,9 +224,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -234,9 +234,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -244,9 +244,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
@@ -254,14 +254,14 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -279,42 +279,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX803: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX900: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX942: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX10: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets_live_vcc
; GFX12: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN implicit [[V_ADD_CO_U32_e64_1]]
%0:vgpr_32, %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN implicit %2
...
@@ -332,42 +332,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, %0
%1:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, %1
SI_RETURN
...
@@ -385,42 +385,42 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__inline_imm_offsets
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = S_ADD_I32 8, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %0
%1:sreg_32 = S_ADD_I32 16, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %1
SI_RETURN
...
@@ -443,9 +443,9 @@ body: |
; GFX803-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX803-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX803-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -454,9 +454,9 @@ body: |
; GFX900-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX900-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -465,9 +465,9 @@ body: |
; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -476,9 +476,9 @@ body: |
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX10-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets
@@ -487,17 +487,17 @@ body: |
; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY1]], %stack.0, implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = COPY $sgpr4
%1:sreg_32 = COPY $sgpr5
%2:sreg_32 = S_ADD_I32 %0, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %2
%3:sreg_32 = S_ADD_I32 %1, %stack.0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %3
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %3
SI_RETURN
...
@@ -520,9 +520,9 @@ body: |
; GFX803-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX803-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX803-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -531,9 +531,9 @@ body: |
; GFX900-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX900-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX900-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -542,9 +542,9 @@ body: |
; GFX942-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX942-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -553,9 +553,9 @@ body: |
; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX10-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__reg_offsets_commute
@@ -564,17 +564,17 @@ body: |
; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr4
; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr5
; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY]], implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 %stack.0, [[COPY1]], implicit-def dead $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN
%0:sreg_32 = COPY $sgpr4
%1:sreg_32 = COPY $sgpr5
%2:sreg_32 = S_ADD_I32 %stack.0, %0, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %2
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %2
%3:sreg_32 = S_ADD_I32 %stack.0, %1, implicit-def dead $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:SREG_32 */, %3
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:SREG_32 */, %3
SI_RETURN
...
@@ -592,48 +592,48 @@ body: |
bb.0:
; GFX803-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX803: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX803-NEXT: S_NOP 0, implicit $scc
; GFX803-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX803-NEXT: SI_RETURN implicit $scc
;
; GFX900-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX900: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX900-NEXT: S_NOP 0, implicit $scc
; GFX900-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX900-NEXT: SI_RETURN implicit $scc
;
; GFX942-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX942: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX942-NEXT: S_NOP 0, implicit $scc
; GFX942-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX942-NEXT: SI_RETURN implicit $scc
;
; GFX10-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX10-NEXT: S_NOP 0, implicit $scc
; GFX10-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX10-NEXT: SI_RETURN implicit $scc
;
; GFX12-LABEL: name: local_stack_alloc__s_add_i32__literal_offsets_live_scc
; GFX12: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_]]
; GFX12-NEXT: S_NOP 0, implicit $scc
; GFX12-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, [[S_ADD_I32_1]]
; GFX12-NEXT: SI_RETURN implicit $scc
%0:sreg_32 = S_ADD_I32 256, %stack.0, implicit-def $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, %0
S_NOP 0, implicit $scc
%1:sreg_32 = S_ADD_I32 512, %stack.0, implicit-def $scc
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2359305 /* reguse:SReg_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3342345 /* reguse:SReg_32 */, %1
SI_RETURN implicit $scc
...
@@ -656,9 +656,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -667,9 +667,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -678,9 +678,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -689,9 +689,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets
@@ -700,15 +700,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %vgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -731,9 +731,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -742,9 +742,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -753,9 +753,9 @@ body: |
; GFX942-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -764,9 +764,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__vgpr_offsets_commute
@@ -775,15 +775,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_MOV_B32_]], %vgpr_offset, implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, %vgpr_offset, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %stack.0, %vgpr_offset, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -805,9 +805,9 @@ body: |
; GFX803-NEXT: {{ $}}
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -815,9 +815,9 @@ body: |
; GFX900-NEXT: {{ $}}
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -825,9 +825,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -836,9 +836,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit-def dead $vcc, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__sgpr_offsets
@@ -848,16 +848,16 @@ body: |
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[COPY]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, [[COPY1]], implicit-def dead $vcc, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_CO_U32_e32 %sgpr_offset, %stack.0, implicit-def dead $vcc, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -880,9 +880,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -891,9 +891,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -903,10 +903,10 @@ body: |
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[COPY]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[COPY1]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -915,9 +915,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets
@@ -926,15 +926,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[S_MOV_B32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, [[S_MOV_B32_]], 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -957,9 +957,9 @@ body: |
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX803-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX803-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX803-NEXT: SI_RETURN
;
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -968,9 +968,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -980,10 +980,10 @@ body: |
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY %sgpr_offset
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[COPY]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY %sgpr_offset
; GFX942-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[COPY1]], 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -992,9 +992,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__sgpr_offsets_commute
@@ -1003,15 +1003,15 @@ body: |
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.0
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_MOV_B32_]], %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_CO_U32_e64_2]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32, dead %2:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
index e4c2d54d9894d..ddb1c210ea5fc 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
@@ -20,16 +20,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX942: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
@@ -37,21 +37,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX12: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e32 256, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 512, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -72,16 +72,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX942: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
@@ -89,21 +89,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX12: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e32 8, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 16, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -124,16 +124,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX942: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
@@ -141,21 +141,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -178,9 +178,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -188,9 +188,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -199,9 +199,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets
@@ -209,15 +209,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %vgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -240,9 +240,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -250,9 +250,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -261,9 +261,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %vgpr_offset, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__vgpr_offsets_commute
@@ -271,15 +271,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %vgpr_offset:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%vgpr_offset:vgpr_32 = COPY $vgpr0
%0:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %stack.0, %vgpr_offset, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -301,9 +301,9 @@ body: |
; GFX900-NEXT: {{ $}}
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX900-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -311,9 +311,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX942-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -322,9 +322,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX10-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, [[V_MOV_B32_e32_]], implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e32__sgpr_offsets
@@ -332,15 +332,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_]]
; GFX12-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e32_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e32 %sgpr_offset, %stack.0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -363,9 +363,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -373,9 +373,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -384,9 +384,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, [[V_MOV_B32_e32_]], 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets
@@ -394,15 +394,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %sgpr_offset, %stack.0, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -425,9 +425,9 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -435,9 +435,9 @@ body: |
; GFX942-NEXT: {{ $}}
; GFX942-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX942-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -446,9 +446,9 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_MOV_B32_e32_]], %sgpr_offset, 0, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__sgpr_offsets_commute
@@ -456,15 +456,15 @@ body: |
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: %sgpr_offset:sreg_32 = COPY $sgpr8
; GFX12-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%sgpr_offset:sreg_32 = COPY $sgpr8
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 %stack.0, %sgpr_offset, 0, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
@@ -486,16 +486,16 @@ body: |
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
- ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX900-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX900-NEXT: SI_RETURN
;
; GFX942-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX942: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 1, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX942-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 1, implicit $exec
- ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX942-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX942-NEXT: SI_RETURN
;
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
@@ -503,21 +503,21 @@ body: |
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[COPY]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
- ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: SI_RETURN
;
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX12: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, 1, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_]]
; GFX12-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 16, %stack.0, 1, implicit $exec
- ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
+ ; GFX12-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
; GFX12-NEXT: SI_RETURN
%0:vgpr_32 = V_ADD_U32_e64 %stack.0, 8, /*clamp*/1, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %0
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %0
%1:vgpr_32 = V_ADD_U32_e64 16, %stack.0, /*clamp*/1, implicit $exec
- INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2228233 /* reguse:VGPR_32 */, %1
+ INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3211273 /* reguse:VGPR_32 */, %1
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
index 24677b60be6c2..1e432a341b647 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
@@ -10,11 +10,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX908: bb.0 (%ir-block.0):
; REGALLOC-GFX908-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX908-NEXT: {{ $}}
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2162697 /* reguse:AGPR_32 */, undef %6:agpr_32
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6094858 /* regdef:VReg_128 */, def %7
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3538954 /* regdef:VReg_64 */, def %8
-
- ; REGALLOC-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64, %7, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %5:agpr_32
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %6
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_64 */, def %7
+ ; REGALLOC-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef %14:vreg_64, %6, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; REGALLOC-GFX908-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
; REGALLOC-GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed renamable $sgpr0_sgpr1_sgpr2_sgpr3
; REGALLOC-GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
@@ -29,14 +28,14 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX908: bb.0 (%ir-block.0):
; PEI-GFX908-NEXT: liveins: $agpr4, $sgpr4_sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9
; PEI-GFX908-NEXT: {{ $}}
- ; PEI-GFX908-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
- ; PEI-GFX908-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
- ; PEI-GFX908-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
- ; PEI-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2162697 /* reguse:AGPR_32 */, undef renamable $agpr0
- ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6094858 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
+ ; PEI-GFX908-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; PEI-GFX908-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $sgpr7, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX908-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef renamable $agpr0
+ ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX908-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
- ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3538954 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1
- ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
+ ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1
+ ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
; PEI-GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1
; PEI-GFX908-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3, implicit $exec
; PEI-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
@@ -56,10 +55,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX90A: bb.0 (%ir-block.0):
; REGALLOC-GFX90A-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX90A-NEXT: {{ $}}
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2162697 /* reguse:AGPR_32 */, undef %6:agpr_32
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6422538 /* regdef:VReg_128_Align2 */, def %7
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3866634 /* regdef:VReg_64_Align2 */, def %8
- ; REGALLOC-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64_align2, %7, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %5:agpr_32
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %6
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_64_Align2 */, def %7
+ ; REGALLOC-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef %14:vreg_64_align2, %6, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; REGALLOC-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
; REGALLOC-GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY killed renamable $sgpr0_sgpr1_sgpr2_sgpr3
; REGALLOC-GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
@@ -73,14 +72,14 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX90A: bb.0 (%ir-block.0):
; PEI-GFX90A-NEXT: liveins: $agpr4, $sgpr4_sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9
; PEI-GFX90A-NEXT: {{ $}}
- ; PEI-GFX90A-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
- ; PEI-GFX90A-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
- ; PEI-GFX90A-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
- ; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 2162697 /* reguse:AGPR_32 */, undef renamable $agpr0
- ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6422538 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
+ ; PEI-GFX90A-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; PEI-GFX90A-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $sgpr7, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX90A-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef renamable $agpr0
+ ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
- ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3866634 /* regdef:VReg_64_Align2 */, def renamable $vgpr0_vgpr1
- ; PEI-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
+ ; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_64_Align2 */, def renamable $vgpr0_vgpr1
+ ; PEI-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
; PEI-GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $agpr0_agpr1_agpr2_agpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; PEI-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
index c90975959c3f4..a81dda3cb4247 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
@@ -37,7 +37,7 @@ body: |
; CHECK-NEXT: dead [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub1:vreg_512 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def dead [[COPY1]], 851978 /* regdef:VGPR_16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def dead [[COPY1]], 1835018 /* regdef:VGPR_16 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub0:vreg_512 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub3:vreg_512 = COPY [[COPY]].sub3
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub2:vreg_512 = COPY undef [[V_MOV_B32_e32_1]]
@@ -63,7 +63,7 @@ body: |
undef %11.sub0:vreg_512 = COPY %4.sub0
%12:vgpr_32 = COPY %4.sub0
%11.sub1:vreg_512 = COPY %4.sub1
- INLINEASM &"", 1, 851978, def dead %12, 851978, def dead %4.sub1, 2147483657, %12, 2147549193, %4.sub1
+ INLINEASM &"", 1, 1835018, def dead %12, 1835018, def dead %4.sub1, 2147483657, %12, 2147549193, %4.sub1
%11.sub2:vreg_512 = COPY undef %1
%11.sub3:vreg_512 = COPY %4.sub3
%11.sub5:vreg_512 = COPY undef %1
diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
index 3ca61d26e8e42..9787bf67918c5 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
@@ -40,18 +40,18 @@ body: |
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def dead %11
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def dead %11
; CHECK-NEXT: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, implicit $exec :: (store (s32), addrspace 1)
; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load (s64), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def %15, 851978 /* regdef:VGPR_16 */, def %16
+ ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def %15, 1835018 /* regdef:VGPR_16 */, def %16
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_2]], 0, 0, implicit $exec
; CHECK-NEXT: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
- ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def %21, 851978 /* regdef:VGPR_16 */, def %22
+ ; CHECK-NEXT: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def %21, 1835018 /* regdef:VGPR_16 */, def %22
; CHECK-NEXT: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_2]], 0, 0, implicit $exec
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def dead [[V_MOV_B32_e32_3]], 851978 /* regdef:VGPR_16 */, def dead [[V_MOV_B32_e32_4]], 851977 /* reguse:VGPR_16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_3]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_4]](tied-def 5), 851977 /* reguse:VGPR_16 */, %15, 851977 /* reguse:VGPR_16 */, %16, 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_2]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def dead [[V_MOV_B32_e32_3]], 1835018 /* regdef:VGPR_16 */, def dead [[V_MOV_B32_e32_4]], 1835017 /* reguse:VGPR_16 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_3]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_4]](tied-def 5), 1835017 /* reguse:VGPR_16 */, %15, 1835017 /* reguse:VGPR_16 */, %16, 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_1]], 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]], 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_3]], 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_2]]
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_1]]
; CHECK-NEXT: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store (s32), addrspace 3)
; CHECK-NEXT: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store (s32), addrspace 3)
@@ -94,21 +94,21 @@ body: |
%10:vgpr_32 = IMPLICIT_DEF
bb.1:
- INLINEASM &"", 1, 851978, def %11:vgpr_32
+ INLINEASM &"", 1, 1835018, def %11:vgpr_32
GLOBAL_STORE_DWORD undef %12:vreg_64, %1, 0, 0, implicit $exec :: (store (s32), addrspace 1)
%13:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load (s64), addrspace 3)
- INLINEASM &"def $0 $1", 1, 851978, def %15:vgpr_32, 851978, def %16:vgpr_32
+ INLINEASM &"def $0 $1", 1, 1835018, def %15:vgpr_32, 1835018, def %16:vgpr_32
%17:vgpr_32 = DS_READ_B32_gfx9 %6, 0, 0, implicit $exec
%18:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
%19:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
- INLINEASM &"def $0 $1", 1, 851978, def %21:vgpr_32, 851978, def %22:vgpr_32
+ INLINEASM &"def $0 $1", 1, 1835018, def %21:vgpr_32, 1835018, def %22:vgpr_32
%23:vgpr_32 = DS_READ_B32_gfx9 %7, 0, 0, implicit $exec
%24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%5.sub1:vreg_64 = COPY %6
%25:vgpr_32 = V_ADD_U32_e32 1, %10, implicit $exec
%26:sreg_64_xexec = V_CMP_GT_U32_e64 64, %25, implicit $exec
%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- INLINEASM &"", 1, 851978, def dead %24, 851978, def dead %27, 851977, %13.sub0, 2147483657, %24(tied-def 3), 2147549193, %27(tied-def 5), 851977, %15, 851977, %16, 851977, %18, 851977, %17, 851977, %23, 851977, %19
+ INLINEASM &"", 1, 1835018, def dead %24, 1835018, def dead %27, 1835017, %13.sub0, 2147483657, %24(tied-def 3), 2147549193, %27(tied-def 5), 1835017, %15, 1835017, %16, 1835017, %18, 1835017, %17, 1835017, %23, 1835017, %19
DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store (s32), addrspace 3)
DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store (s32), addrspace 3)
DS_WRITE_B64_gfx9 undef %30:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
index bd255e88b9512..7dc0a92c906f6 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
@@ -12,10 +12,10 @@ define amdgpu_kernel void @test_spill_av_class(<4 x i32> %arg) #0 {
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
; GCN-NEXT: [[V_MFMA_I32_4X4X4I8_e64_:%[0-9]+]]:areg_128 = V_MFMA_I32_4X4X4I8_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2228234 /* regdef:VGPR_32 */, def undef %14.sub0
+ ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3211274 /* regdef:VGPR_32 */, def undef %13.sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_I32_4X4X4I8_e64_]]
- ; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %24:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
- ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3538953 /* reguse:VReg_64 */, %14
+ ; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %23:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4521993 /* reguse:VReg_64 */, %13
; GCN-NEXT: S_ENDPGM 0
%v0 = call i32 asm sideeffect "; def $0", "=v"()
%tmp = insertelement <2 x i32> poison, i32 %v0, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
index b428e859a6d32..40c0e5b17f8d8 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+++ b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
@@ -28,9 +28,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def [[V_MOV_B32_e32_]], 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub0, 851978 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub1
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def [[V_MOV_B32_e32_]], 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub0, 1835018 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -41,9 +41,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
- INLINEASM &"", 1, 851977, %2
- INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def %0.sub1
+ INLINEASM &"", 1, 1835018, def %0, 2147549193, %0(tied-def 3)
+ INLINEASM &"", 1, 1835017, %2
+ INLINEASM &"", 1, 1835018, def undef %0.sub0, 1835018, def %0.sub1
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
@@ -69,9 +69,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def [[V_MOV_B32_e32_]], 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub1, 851978 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def [[V_MOV_B32_e32_]], 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835017 /* reguse:VGPR_16 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 1835018 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub1, 1835018 /* regdef:VGPR_16 */, def undef [[V_MOV_B32_e32_]].sub0
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -82,9 +82,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
- INLINEASM &"", 1, 851977, %2
- INLINEASM &"", 1, 851978, def %0.sub1, 851978, def undef %0.sub0
+ INLINEASM &"", 1, 1835018, def %0, 2147549193, %0(tied-def 3)
+ INLINEASM &"", 1, 1835017, %2
+ INLINEASM &"", 1, 1835018, def %0.sub1, 1835018, def undef %0.sub0
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
index f590324f1120d..925622148a561 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
@@ -7,16 +7,16 @@ define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8
; CHECK-NEXT: t4: i32,ch = CopyFromReg # D:1 t0, Register:i32 %9
-; CHECK-NEXT: t50: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<60>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11>
-; CHECK-NEXT: t27: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
-; CHECK-NEXT: t30: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
-; CHECK-NEXT: t33: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<60>, t27, TargetConstant:i32<3>, t30, TargetConstant:i32<11>
-; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t50, t33
-; CHECK-NEXT: t24: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3>
-; CHECK-NEXT: t17: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t24
-; CHECK-NEXT: t39: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11>
-; CHECK-NEXT: t19: ch,glue = CopyToReg # D:1 t17, Register:i32 $vgpr1, t39, t17:1
-; CHECK-NEXT: t20: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t19, t19:1
+; CHECK-NEXT: t49: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11>
+; CHECK-NEXT: t26: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
+; CHECK-NEXT: t29: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
+; CHECK-NEXT: t32: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t26, TargetConstant:i32<3>, t29, TargetConstant:i32<11>
+; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t49, t32
+; CHECK-NEXT: t23: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3>
+; CHECK-NEXT: t16: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t23
+; CHECK-NEXT: t38: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11>
+; CHECK-NEXT: t18: ch,glue = CopyToReg # D:1 t16, Register:i32 $vgpr1, t38, t16:1
+; CHECK-NEXT: t19: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t18, t18:1
; CHECK-EMPTY:
%loc = alloca i64, addrspace(5)
%j = load i64, ptr addrspace(5) %loc
>From ef7494c60405234e6f3165c687917dc1320b9721 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 6 May 2025 11:45:11 -0700
Subject: [PATCH 2/9] Fix for other (besides image_atomic_*) mimg instructions.
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 8 +-
llvm/test/MC/AMDGPU/gfx8_asm_mimg.s | 174 +++++++++++++++++++++
2 files changed, 178 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 91756b9fd6678..f27c887b0a03b 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -424,7 +424,7 @@ class MIMG_NoSampler_Helper <mimgopc op, string asm,
RegisterClass addr_rc,
string dns="">
: MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> {
- let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
+ let InOperandList = !con((ins addr_rc:$vaddr, SReg_RSRC:$srsrc,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -681,7 +681,7 @@ class MIMG_Store_Helper <mimgopc op, string asm,
RegisterClass addr_rc,
string dns = "">
: MIMG_gfx6789<op.GFX10M, (outs), dns> {
- let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
+ let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_RSRC:$srsrc,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -923,7 +923,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
!if(enableDisasm, "GFX10", "")> {
let Constraints = "$vdst = $vdata";
- let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
+ let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -1130,7 +1130,7 @@ multiclass MIMG_Atomic_Renamed <mimgopc op, string asm, string renamed,
class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterClass dst_rc,
RegisterClass src_rc, string dns="">
: MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
- let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
+ let InOperandList = !con((ins src_rc:$vaddr, SReg_RSRC:$srsrc, SReg_128_XNULL:$ssamp,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
index d5dcf4f3a7e08..d9600fd638c19 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
@@ -24,6 +24,9 @@ image_load v5, v1, s[8:15] dmask:0x2
image_load v[5:6], v1, s[8:15] dmask:0x3
// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+image_load v[5:6], v1, s[8:11] dmask:0x3 r128
+// CHECK: [0x00,0x83,0x00,0xf0,0x01,0x05,0x02,0x00]
+
image_load v5, v1, s[8:15] dmask:0x4
// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
@@ -96,6 +99,9 @@ image_load v5, v1, s[8:15] dmask:0x1 d16
image_load_mip v5, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+image_load_mip v5, v[1:2], s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x04,0xf0,0x01,0x05,0x02,0x00]
+
image_load_mip v252, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
@@ -117,6 +123,9 @@ image_load_mip v5, v[1:2], s[8:15] dmask:0x2
image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3
// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
+image_load_mip v[5:6], v[1:2], s[8:11] dmask:0x3 r128
+// CHECK: [0x00,0x83,0x04,0xf0,0x01,0x05,0x02,0x00]
+
image_load_mip v5, v[1:2], s[8:15] dmask:0x4
// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
@@ -186,6 +195,9 @@ image_load_mip v5, v[1:2], s[8:15] dmask:0x1 d16
image_load_pck v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+image_load_pck v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x08,0xf0,0x01,0x05,0x02,0x00]
+
image_load_pck v252, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x08,0xf0,0x01,0xfc,0x02,0x00]
@@ -276,6 +288,9 @@ image_load_pck v5, v1, s[8:15] dmask:0x1 da
image_load_pck_sgn v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+image_load_pck_sgn v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
image_load_pck_sgn v252, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0xfc,0x02,0x00]
@@ -366,6 +381,9 @@ image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 da
image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+image_load_mip_pck v5, v[1:2], s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x10,0xf0,0x01,0x05,0x02,0x00]
+
image_load_mip_pck v252, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x10,0xf0,0x01,0xfc,0x02,0x00]
@@ -453,6 +471,9 @@ image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 da
image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+image_load_mip_pck_sgn v5, v[1:2], s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x14,0xf0,0x01,0x05,0x02,0x00]
+
image_load_mip_pck_sgn v252, v[1:2], s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x14,0xf0,0x01,0xfc,0x02,0x00]
@@ -540,6 +561,9 @@ image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 da
image_store v1, v2, s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+image_store v1, v2, s[12:15] dmask:0x1 unorm r128
+// CHECK: [0x00,0x91,0x20,0xf0,0x02,0x01,0x03,0x00]
+
image_store v252, v2, s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
@@ -627,6 +651,9 @@ image_store v1, v2, s[12:19] dmask:0x1 unorm d16
image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+image_store_mip v1, v[2:3], s[12:15] dmask:0x1 unorm r128
+// CHECK: [0x00,0x91,0x24,0xf0,0x02,0x01,0x03,0x00]
+
image_store_mip v252, v[2:3], s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
@@ -711,6 +738,9 @@ image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm d16
image_store_pck v1, v2, s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+image_store_pck v1, v2, s[12:15] dmask:0x1 unorm r128
+// CHECK: [0x00,0x91,0x28,0xf0,0x02,0x01,0x03,0x00]
+
image_store_pck v252, v2, s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x28,0xf0,0x02,0xfc,0x03,0x00]
@@ -795,6 +825,9 @@ image_store_pck v1, v2, s[12:19] dmask:0x1 unorm da
image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+image_store_mip_pck v1, v[2:3], s[12:15] dmask:0x1 unorm r128
+// CHECK: [0x00,0x91,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
@@ -876,6 +909,9 @@ image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm da
image_get_resinfo v5, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
+image_get_resinfo v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x38,0xf0,0x01,0x05,0x02,0x00]
+
image_get_resinfo v252, v1, s[8:15] dmask:0x1
// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
@@ -1080,6 +1116,9 @@ image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_add v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x48,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
@@ -1122,6 +1161,9 @@ image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x4c,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_sub v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
@@ -1164,6 +1206,9 @@ image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x50,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_smin v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x50,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
@@ -1206,6 +1251,9 @@ image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x54,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_umin v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x54,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
@@ -1248,6 +1296,9 @@ image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x58,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_smax v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x58,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
@@ -1290,6 +1341,9 @@ image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
@@ -1332,6 +1386,9 @@ image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x60,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_and v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x60,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
@@ -1374,6 +1431,9 @@ image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x64,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_or v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x64,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
@@ -1416,6 +1476,9 @@ image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x68,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_xor v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x68,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
@@ -1458,6 +1521,9 @@ image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x6c,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_inc v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
@@ -1500,6 +1566,9 @@ image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x70,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_dec v5, v1, s[8:11] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x70,0xf0,0x01,0x05,0x02,0x00]
+
image_sample v5, v1, s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
@@ -1599,6 +1668,9 @@ image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 da
image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 d16
// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x80]
+image_sample v5, v1, s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x80,0xf0,0x01,0x05,0x62,0x00]
+
image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
@@ -4638,6 +4710,9 @@ image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x00,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4 v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
@@ -4692,9 +4767,15 @@ image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x80]
+image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x00,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_cl v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x04,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_cl v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
@@ -4752,6 +4833,9 @@ image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_l v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x10,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_l v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
@@ -4809,6 +4893,9 @@ image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_b v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x14,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_b v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
@@ -4866,6 +4953,9 @@ image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_b_cl v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x18,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
@@ -4923,6 +5013,9 @@ image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_lz v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_lz v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
@@ -4980,6 +5073,9 @@ image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x20,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
@@ -5037,6 +5133,9 @@ image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_cl v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x24,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
@@ -5094,6 +5193,9 @@ image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_l v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x30,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
@@ -5151,6 +5253,9 @@ image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_b v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x34,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
@@ -5208,6 +5313,9 @@ image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x38,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_b_cl v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
@@ -5262,6 +5370,9 @@ image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_lz v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_lz v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
@@ -5319,6 +5430,9 @@ image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_o v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x40,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
@@ -5376,6 +5490,9 @@ image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_cl_o v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x44,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
@@ -5433,6 +5550,9 @@ image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_l_o v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x50,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
@@ -5490,6 +5610,9 @@ image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_b_o v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x54,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
@@ -5547,6 +5670,9 @@ image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x58,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
@@ -5601,6 +5727,9 @@ image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_lz_o v[5:8], v[1:3], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_lz_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
@@ -5658,6 +5787,9 @@ image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_o v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x60,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
@@ -5715,6 +5847,9 @@ image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x64,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
@@ -5769,6 +5904,9 @@ image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_l_o v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x70,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_l_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
@@ -5823,6 +5961,9 @@ image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_b_o v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x74,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_b_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
@@ -5877,6 +6018,9 @@ image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x78,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
@@ -5931,6 +6075,9 @@ image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
@@ -6030,6 +6177,9 @@ image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
+image_get_lod v[5:7], v1, s[8:11], s[12:15] dmask:0x7 r128
+// CHECK: [0x00,0x87,0x80,0xf1,0x01,0x05,0x62,0x00]
+
image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
@@ -6126,6 +6276,9 @@ image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
// CHECK: [0x00,0x07,0xa0,0xf1,0x01,0x05,0x62,0x00]
+image_sample_cd v[5:7], v[1:3], s[8:11], s[12:15] dmask:0x7 r128
+// CHECK: [0x00,0x87,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x8
// CHECK: [0x00,0x08,0xa0,0xf1,0x01,0x05,0x62,0x00]
@@ -6228,6 +6381,9 @@ image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
// CHECK: [0x00,0x07,0xa4,0xf1,0x01,0x05,0x62,0x00]
+image_sample_cd_cl v[5:7], v[1:4], s[8:11], s[12:15] dmask:0x7 r128
+// CHECK: [0x00,0x87,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
// CHECK: [0x00,0x08,0xa4,0xf1,0x01,0x05,0x62,0x00]
@@ -6285,6 +6441,9 @@ image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+image_sample_c_cd v5, v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_c_cd v252, v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0xfc,0x62,0x00]
@@ -6384,6 +6543,9 @@ image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+image_sample_c_cd_cl v5, v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xac,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_c_cd_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xac,0xf1,0x01,0xfc,0x62,0x00]
@@ -6480,6 +6642,9 @@ image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+image_sample_cd_o v5, v[1:4], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_cd_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0xfc,0x62,0x00]
@@ -6579,6 +6744,9 @@ image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+image_sample_cd_cl_o v5, v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0xfc,0x62,0x00]
@@ -6675,6 +6843,9 @@ image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+image_sample_c_cd_o v5, v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_c_cd_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0xfc,0x62,0x00]
@@ -6771,6 +6942,9 @@ image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+image_sample_c_cd_cl_o v5, v[1:8], s[8:11], s[12:15] dmask:0x1 r128
+// CHECK: [0x00,0x81,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
image_sample_c_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0xfc,0x62,0x00]
>From 0eac0e83e3b4690cc6b455e88a8ca73633259e41 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 6 May 2025 15:16:58 -0700
Subject: [PATCH 3/9] For gfx10.
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 14 ++--
llvm/test/MC/AMDGPU/gfx10_asm_mimg.s | 75 ++++++++++++++++++++++
2 files changed, 82 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index f27c887b0a03b..0eaae474f193a 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -449,7 +449,7 @@ class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
RegisterClass DataRC, RegisterClass AddrRC,
string dns="">
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
- let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
+ let InOperandList = !con((ins AddrRC:$vaddr0, SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -462,7 +462,7 @@ class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
string dns="">
: MIMG_nsa_gfx10<op.GFX10M, (outs DataRC:$vdata), num_addrs, dns> {
let InOperandList = !con(AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -707,7 +707,7 @@ class MIMG_Store_gfx10<mimgopc op, string opcode,
RegisterClass DataRC, RegisterClass AddrRC,
string dns="">
: MIMG_gfx10<op.GFX10M, (outs), dns> {
- let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
+ let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -721,7 +721,7 @@ class MIMG_Store_nsa_gfx10<mimgopc op, string opcode,
: MIMG_nsa_gfx10<op.GFX10M, (outs), num_addrs, dns> {
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -923,7 +923,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
!if(enableDisasm, "GFX10", "")> {
let Constraints = "$vdst = $vdata";
- let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
+ let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -938,7 +938,7 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe));
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -1151,7 +1151,7 @@ class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterClass dst_rc,
class MIMG_Sampler_OpList_gfx10p<dag OpPrefix, bit HasD16> {
dag ret = !con(OpPrefix,
- (ins SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
+ (ins SReg_RSRC:$srsrc, SReg_128_XNULL:$ssamp,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(HasD16, (ins D16:$d16), (ins)));
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
index 6039e4abf5d96..172a4766256ca 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
@@ -3,6 +3,9 @@
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00]
+image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D unorm r128
+; GFX10: image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D unorm r128 ; encoding: [0x00,0x9f,0x00,0xf0,0x00,0x00,0x00,0x00]
+
image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
; GFX10: image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x0a,0x1f,0x00,0xf0,0x02,0x01,0x01,0x00,0x03,0x00,0x00,0x00]
@@ -88,57 +91,108 @@ image_load_mip v255, [v254, v255, v253, v255], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_
image_store v[0:3], [v254, v255, v253, v255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
; GFX10: image_store v[0:3], [v254, v255, v253, v255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x3a,0x0f,0x20,0xf0,0xfe,0x00,0x18,0x00,0xff,0xfd,0xff,0x00]
+image_store v[0:3], [v254, v255, v253, v255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128
+; GFX10: image_store v[0:3], [v254, v255, v253, v255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128 ; encoding: [0x3a,0x8f,0x20,0xf0,0xfe,0x00,0x18,0x00,0xff,0xfd,0xff,0x00]
+
image_store v[0:3], v[254:255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10: image_store v[0:3], v[254:255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x20,0xf0,0xfe,0x00,0x18,0x00]
image_store_mip v[0:3], v[253:255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D
; GFX10: image_store_mip v[0:3], v[253:255], s[96:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x24,0xf0,0xfd,0x00,0x18,0x00]
+image_store_mip v[0:3], v[253:255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D r128
+; GFX10: image_store_mip v[0:3], v[253:255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x08,0x8f,0x24,0xf0,0xfd,0x00,0x18,0x00]
+
image_get_resinfo v[4:7], v32, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_3D
; GFX10: image_get_resinfo v[4:7], v32, s[96:103] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x10,0x0f,0x38,0xf0,0x20,0x04,0x18,0x00]
+image_get_resinfo v[4:7], v32, s[96:99] dmask:0xf dim:SQ_RSRC_IMG_3D r128
+; GFX10: image_get_resinfo v[4:7], v32, s[96:99] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x10,0x8f,0x38,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_swap v4, v[32:34], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_3D glc
; GFX10: image_atomic_swap v4, v[32:34], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_3D glc ; encoding: [0x10,0x21,0x3c,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_swap v4, v[32:34], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_3D glc r128
+; GFX10: image_atomic_swap v4, v[32:34], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_3D glc r128 ; encoding: [0x10,0xa1,0x3c,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_3D glc
; GFX10: image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_3D glc ; encoding: [0x12,0x23,0x40,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_3D glc r128
+; GFX10: image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_3D glc r128 ; encoding: [0x12,0xa3,0x40,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+
image_atomic_add v[4:5], [v32, v1, v2], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_CUBE glc
; GFX10: image_atomic_add v[4:5], [v32, v1, v2], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_CUBE glc ; encoding: [0x1a,0x23,0x44,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+image_atomic_add v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_CUBE glc r128
+; GFX10: image_atomic_add v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_CUBE glc r128 ; encoding: [0x1a,0xa3,0x44,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+
image_atomic_sub v4, [v32, v1], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY glc
; GFX10: image_atomic_sub v4, [v32, v1], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY glc ; encoding: [0x22,0x21,0x48,0xf0,0x20,0x04,0x18,0x00,0x01,0x00,0x00,0x00]
+image_atomic_sub v4, [v32, v1], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY glc r128
+; GFX10: image_atomic_sub v4, [v32, v1], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY glc r128 ; encoding: [0x22,0xa1,0x48,0xf0,0x20,0x04,0x18,0x00,0x01,0x00,0x00,0x00]
+
image_atomic_smin v4, [v32, v1, v2], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY glc
; GFX10: image_atomic_smin v4, [v32, v1, v2], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY glc ; encoding: [0x2a,0x21,0x50,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+image_atomic_smin v4, [v32, v1, v2], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY glc r128
+; GFX10: image_atomic_smin v4, [v32, v1, v2], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY glc r128 ; encoding: [0x2a,0xa1,0x50,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+
image_atomic_umin v4, [v32, v1, v2], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA glc
; GFX10: image_atomic_umin v4, [v32, v1, v2], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA glc ; encoding: [0x32,0x21,0x54,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+image_atomic_umin v4, [v32, v1, v2], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA glc r128
+; GFX10: image_atomic_umin v4, [v32, v1, v2], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA glc r128 ; encoding: [0x32,0xa1,0x54,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+
image_atomic_smax v4, [v32, v1, v2, v3], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY glc
; GFX10: image_atomic_smax v4, [v32, v1, v2, v3], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY glc ; encoding: [0x3a,0x21,0x58,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x03,0x00]
+image_atomic_smax v4, [v32, v1, v2, v3], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY glc r128
+; GFX10: image_atomic_smax v4, [v32, v1, v2, v3], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY glc r128 ; encoding: [0x3a,0xa1,0x58,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x03,0x00]
+
image_atomic_umax v4, [v32, v1], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D glc
; GFX10: image_atomic_umax v4, [v32, v1], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D glc ; encoding: [0x0a,0x21,0x5c,0xf0,0x20,0x04,0x18,0x00,0x01,0x00,0x00,0x00]
+image_atomic_umax v4, [v32, v1], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D glc r128
+; GFX10: image_atomic_umax v4, [v32, v1], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D glc r128 ; encoding: [0x0a,0xa1,0x5c,0xf0,0x20,0x04,0x18,0x00,0x01,0x00,0x00,0x00]
+
image_atomic_and v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_and v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x60,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_and v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_and v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x60,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_or v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_or v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x64,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_or v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_or v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x64,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x68,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_xor v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_xor v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x68,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_inc v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_inc v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x6c,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_inc v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_inc v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x6c,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x70,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_dec v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_dec v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x70,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_fcmpswap v[4:5], v32, s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa3,0x74,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_fcmpswap v[254:255], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
; GFX10: [0x00,0x13,0x74,0xf0,0x02,0xfe,0x03,0x00]
@@ -262,15 +316,27 @@ image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm lw
image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_fmin v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_fmin v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x78,0xf0,0x20,0x04,0x18,0x00]
+
image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
; GFX10: image_atomic_fmax v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x7c,0xf0,0x20,0x04,0x18,0x00]
+image_atomic_fmax v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128
+; GFX10: image_atomic_fmax v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D glc r128 ; encoding: [0x00,0xa1,0x7c,0xf0,0x20,0x04,0x18,0x00]
+
image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D
; GFX10: image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x07,0x80,0xf0,0x20,0x40,0x21,0x03]
+image_sample v[64:66], v32, s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128
+; GFX10: image_sample v[64:66], v32, s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x87,0x80,0xf0,0x20,0x40,0x21,0x03]
+
image_sample_cl v[64:66], [v32, v16], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D
; GFX10: image_sample_cl v[64:66], [v32, v16], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x07,0x84,0xf0,0x20,0x40,0x21,0x03,0x10,0x00,0x00,0x00]
+image_sample_cl v[64:66], [v32, v16], s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128
+; GFX10: image_sample_cl v[64:66], [v32, v16], s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x02,0x87,0x84,0xf0,0x20,0x40,0x21,0x03,0x10,0x00,0x00,0x00]
+
image_sample_cl v[64:66], [v32, v16, v15], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
; GFX10: image_sample_cl v[64:66], [v32, v16, v15], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x0a,0x07,0x84,0xf0,0x20,0x40,0x21,0x03,0x10,0x0f,0x00,0x00]
@@ -289,6 +355,9 @@ image_sample_cl v[64:66], [v32, v16, v20, v21], s[4:11], s[100:103] dmask:0x7 di
image_sample_d v[64:66], [v32, v16, v8], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D
; GFX10: image_sample_d v[64:66], [v32, v16, v8], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x07,0x88,0xf0,0x20,0x40,0x21,0x03,0x10,0x08,0x00,0x00]
+image_sample_d v[64:66], [v32, v16, v8], s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128
+; GFX10: image_sample_d v[64:66], [v32, v16, v8], s[4:7], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x02,0x87,0x88,0xf0,0x20,0x40,0x21,0x03,0x10,0x08,0x00,0x00]
+
image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
; GFX10: image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x0c,0x07,0x88,0xf0,0x20,0x40,0x21,0x03,0x10,0x08,0x04,0x02,0x01,0x00,0x00,0x00]
@@ -400,6 +469,9 @@ image_sample_c_lz_o v[64:66], [v32, v0, v16], s[4:11], s[100:103] dmask:0x7 dim:
image_gather4 v[64:67], v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX10: image_gather4 v[64:67], v32, s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x01,0x00,0xf1,0x20,0x40,0x21,0x03]
+image_gather4 v[64:67], v32, s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+; GFX10: image_gather4 v[64:67], v32, s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf1,0x20,0x40,0x21,0x03]
+
image_gather4_cl v[64:67], v[32:35], s[4:11], s[100:103] dmask:0x2 dim:SQ_RSRC_IMG_CUBE
; GFX10: image_gather4_cl v[64:67], v[32:35], s[4:11], s[100:103] dmask:0x2 dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x02,0x04,0xf1,0x20,0x40,0x21,0x03]
@@ -475,6 +547,9 @@ image_gather4h v[64:67], [v32, v33, v34], s[4:11], s[4:7] dmask:0x2 dim:SQ_RSRC_
image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX10: image_get_lod v64, v[32:33], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x80,0xf1,0x20,0x40,0x21,0x03]
+image_get_lod v64, v[32:33], s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
+; GFX10: image_get_lod v64, v[32:33], s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x08,0x81,0x80,0xf1,0x20,0x40,0x21,0x03]
+
image_get_lod v[64:65], [v32, v0, v16], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX10: image_get_lod v[64:65], [v32, v0, v16], s[4:11], s[100:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x2a,0x03,0x80,0xf1,0x20,0x40,0x21,0x03,0x00,0x10,0x00,0x00]
>From a503c3cfe53cdfd0191a2d6e4d4fec470e21833f Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 6 May 2025 15:56:00 -0700
Subject: [PATCH 4/9] For gfx11.
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 12 +++++------
llvm/test/MC/AMDGPU/gfx11_asm_mimg.s | 24 ++++++++++++++++++++++
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 0eaae474f193a..733cf7fb5c3be 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -474,7 +474,7 @@ class MIMG_NoSampler_gfx11<mimgopc op, string opcode,
RegisterClass DataRC, RegisterClass AddrRC,
string dns="">
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
- let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
+ let InOperandList = !con((ins AddrRC:$vaddr0, SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -487,7 +487,7 @@ class MIMG_NoSampler_nsa_gfx11<mimgopc op, string opcode,
string dns="">
: MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns> {
let InOperandList = !con(AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -733,7 +733,7 @@ class MIMG_Store_gfx11<mimgopc op, string opcode,
RegisterClass DataRC, RegisterClass AddrRC,
string dns="">
: MIMG_gfx11<op.GFX11, (outs), dns> {
- let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
+ let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -747,7 +747,7 @@ class MIMG_Store_nsa_gfx11<mimgopc op, string opcode,
: MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns> {
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
@@ -951,7 +951,7 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
!if(enableDisasm, "GFX11", "")> {
let Constraints = "$vdst = $vdata";
- let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256_XNULL:$srsrc,
+ let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_RSRC:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe);
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
@@ -966,7 +966,7 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$srsrc, DMask:$dmask,
+ (ins SReg_RSRC:$srsrc, DMask:$dmask,
Dim:$dim, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe));
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe";
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
index 88deaeff19fa3..2f3f844abdab6 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg.s
@@ -3,6 +3,9 @@
image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
// GFX11: [0x80,0x03,0x30,0xf0,0x02,0x01,0x03,0x00]
+image_atomic_add v[1:2], v2, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm r128
+// GFX11: [0x80,0x83,0x30,0xf0,0x02,0x01,0x03,0x00]
+
image_atomic_add v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
// GFX11: [0x80,0x03,0x30,0xf0,0xff,0x01,0x03,0x00]
@@ -1275,6 +1278,9 @@ image_bvh_intersect_ray v[252:255], v[248:255], ttmp[12:15] a16
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D
// GFX11: [0x04,0x04,0xbc,0xf0,0x01,0x05,0x02,0x0c]
+image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D r128
+// GFX11: [0x04,0x84,0xbc,0xf0,0x01,0x05,0x02,0x0c]
+
image_gather4 v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x4 dim:SQ_RSRC_IMG_2D
// GFX11: [0x04,0x04,0xbc,0xf0,0xfe,0x05,0x02,0x0c]
@@ -1815,6 +1821,9 @@ image_gather4h v[254:255], v[254:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_
image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0xe0,0xf0,0x01,0x05,0x02,0x0c]
+image_get_lod v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
+// GFX11: [0x00,0x83,0xe0,0xf0,0x01,0x05,0x02,0x0c]
+
image_get_lod v[5:6], v255, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0xe0,0xf0,0xff,0x05,0x02,0x0c]
@@ -1887,6 +1896,9 @@ image_get_lod v[254:255], v[254:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_R
image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x5c,0xf0,0x01,0x05,0x02,0x00]
+image_get_resinfo v[5:6], v1, s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
+// GFX11: [0x00,0x83,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
image_get_resinfo v[5:6], v255, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x5c,0xf0,0xff,0x05,0x02,0x00]
@@ -1959,6 +1971,9 @@ image_get_resinfo v[254:255], v255, ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRA
image_load v[5:6], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+image_load v[5:6], v1, s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
+// GFX11: [0x00,0x83,0x00,0xf0,0x01,0x05,0x02,0x00]
+
image_load v[5:6], v255, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x00,0xf0,0xff,0x05,0x02,0x00]
@@ -2463,6 +2478,9 @@ image_load_pck_sgn v[254:255], v[254:255], ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_
image_msaa_load v[5:8], v[1:4], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
// GFX11: [0x1c,0x04,0x60,0xf0,0x01,0x05,0x02,0x00]
+image_msaa_load v[5:8], v[1:4], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128
+// GFX11: [0x1c,0x84,0x60,0xf0,0x01,0x05,0x02,0x00]
+
image_msaa_load v[252:255], v[252:255], s[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
// GFX11: [0x1c,0x04,0x60,0xf0,0xfc,0xfc,0x02,0x00]
@@ -2487,6 +2505,9 @@ image_msaa_load v[253:255], v[254:255], ttmp[8:15] dmask:0x4 dim:SQ_RSRC_IMG_2D_
image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x6c,0xf0,0x01,0x05,0x02,0x0c]
+image_sample v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
+// GFX11: [0x00,0x83,0x6c,0xf0,0x01,0x05,0x02,0x0c]
+
image_sample v[5:6], v255, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
// GFX11: [0x00,0x03,0x6c,0xf0,0xff,0x05,0x02,0x0c]
@@ -5271,6 +5292,9 @@ image_sample_o v[254:255], v[253:255], ttmp[8:15], ttmp[12:15] dmask:0x4 dim:SQ_
image_store v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
// GFX11: [0x80,0x03,0x18,0xf0,0x02,0x01,0x03,0x00]
+image_store v[1:2], v2, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm r128
+// GFX11: [0x80,0x83,0x18,0xf0,0x02,0x01,0x03,0x00]
+
image_store v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
// GFX11: [0x80,0x03,0x18,0xf0,0xff,0x01,0x03,0x00]
>From 5c3b75e158acda1275b8a80cd8b357097a7c7f66 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 6 May 2025 16:17:27 -0700
Subject: [PATCH 5/9] For gfx12.
---
llvm/lib/Target/AMDGPU/MIMGInstructions.td | 10 +++++-----
llvm/test/MC/AMDGPU/gfx12_asm_vimage.s | 12 ++++++++++++
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 733cf7fb5c3be..97f4820272ef0 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -500,7 +500,7 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
string dns="">
: VIMAGE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns> {
let InOperandList = !con(AddrIns,
- (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+ (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -512,7 +512,7 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
string dns="">
: VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
let InOperandList = !con(AddrIns,
- (ins SReg_256_XNULL:$rsrc),
+ (ins SReg_RSRC:$rsrc),
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
(ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
@@ -529,7 +529,7 @@ class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
string dns="">
: VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
let InOperandList = !con(AddrIns,
- (ins SReg_256_XNULL:$rsrc),
+ (ins SReg_RSRC:$rsrc),
!if(BaseOpcode.Sampler, (ins SReg_128_XNULL:$samp), (ins)),
(ins DMask:$dmask, Dim:$dim, UNorm:$unorm,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
@@ -761,7 +761,7 @@ class VIMAGE_Store_gfx12<mimgopc op, string opcode,
: VIMAGE_gfx12<op.GFX12, (outs), num_addrs, dns> {
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+ (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
let AsmString = opcode#" $vdata, "#AddrAsm#", $rsrc$dmask$dim$cpol$r128$a16$tfe"
@@ -980,7 +980,7 @@ class VIMAGE_Atomic_gfx12<mimgopc op, string opcode, RegisterClass DataRC,
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
- (ins SReg_256_XNULL:$rsrc, DMask:$dmask, Dim:$dim,
+ (ins SReg_RSRC:$rsrc, DMask:$dmask, Dim:$dim,
CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe));
let AsmString = !if(!empty(renamed), opcode, renamed)#" $vdata, "#AddrAsm#
", $rsrc$dmask$dim$cpol$r128$a16$tfe";
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
index 1a3baed75efbb..1f91e3b955eba 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
@@ -3,6 +3,9 @@
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
// GFX12: encoding: [0x00,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
image_load v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
// GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
@@ -287,6 +290,9 @@ image_load_mip_pck_sgn v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_
image_store v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
// GFX12: encoding: [0x00,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+image_store v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
image_store v[1:4], [v2, v3], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
// GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
@@ -495,6 +501,9 @@ image_store_mip_pck v5, [v0, v1], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STO
image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
// GFX12: encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+image_atomic_swap v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+
image_atomic_swap v1, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
// GFX12: encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
@@ -1075,6 +1084,9 @@ image_bvh8_intersect_ray v[0:9], [v[0:1], v[11:12], v[3:5], v[6:8], v9], s[0:3]
image_get_resinfo v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D
// GFX12: encoding: [0x00,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+image_get_resinfo v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// GFX12: encoding: [0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+
image_get_resinfo v4, v32, s[96:103] dmask:0x2 dim:SQ_RSRC_IMG_2D
// GFX12: encoding: [0x01,0xc0,0x85,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
>From 73836d7c7be01b86f4326fa50273b0b3df77d49c Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 7 May 2025 16:33:49 -0700
Subject: [PATCH 6/9] Ensure consistency between rsrc reg size and the r128
flag.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 69 +++++++++++++++++--
llvm/test/MC/AMDGPU/gfx10_asm_mimg.s | 5 +-
llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s | 30 ++++++++
llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s | 5 +-
llvm/test/MC/AMDGPU/gfx12_asm_vimage.s | 20 +++---
llvm/test/MC/AMDGPU/gfx12_asm_vsample.s | 15 ++--
llvm/test/MC/AMDGPU/gfx8_asm_mimg.s | 4 +-
llvm/test/MC/AMDGPU/mimg-err.s | 54 +++++++++++++++
llvm/test/MC/AMDGPU/mimg.s | 36 +++++-----
9 files changed, 183 insertions(+), 55 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 7467d58ffe5d2..9596fe3709a44 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1781,6 +1781,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool validateMIMGD16(const MCInst &Inst);
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
bool validateMIMGMSAA(const MCInst &Inst);
+ bool validateMIMGR128(const MCInst &Inst, const OperandVector &Operands);
bool validateOpSel(const MCInst &Inst);
bool validateTrue16OpSel(const MCInst &Inst);
bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
@@ -3974,6 +3975,64 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
return false;
}
+bool AMDGPUAsmParser::validateMIMGR128(const MCInst &Inst,
+ const OperandVector &Operands) {
+ const unsigned Opc = Inst.getOpcode();
+ const MCInstrDesc &Desc = MII.get(Opc);
+
+ if ((Desc.TSFlags & MIMGFlags) == 0)
+ return true;
+
+ // image_bvh_intersect_ray instructions only support 128b RSRC reg
+ if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH)
+ return true;
+
+ AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
+ ? AMDGPU::OpName::srsrc
+ : AMDGPU::OpName::rsrc;
+ int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
+ assert(SrsrcIdx != -1);
+
+ auto RsrcReg = Inst.getOperand(SrsrcIdx).getReg();
+
+ unsigned SrsrcRegSize = 4;
+ if (getMRI()->getRegClass(AMDGPU::SReg_256_XNULLRegClassID).contains(RsrcReg))
+ SrsrcRegSize = 8;
+ else {
+ switch (RsrcReg.id()) {
+ case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_vi:
+ case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_vi:
+ case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_vi:
+ case TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_gfx9plus:
+ case TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_gfx9plus:
+ case TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15_gfx9plus:
+ SrsrcRegSize = 8;
+ break;
+ default:
+ break;
+ }
+ }
+
+ int R128Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::r128);
+ bool IsR128 =
+ (hasMIMG_R128() && R128Idx != -1 && Inst.getOperand(R128Idx).getImm());
+
+ if (SrsrcRegSize == 8 && IsR128) {
+ auto Loc = getImmLoc(AMDGPUOperand::ImmTyR128A16, Operands);
+ Error(Loc, "r128 not allowed with 256-bit RSRC reg");
+ return false;
+ } else if (SrsrcRegSize == 4 && !IsR128) {
+ auto Loc = getInstLoc(Operands);
+ if (hasMIMG_R128())
+ Error(Loc,
+ "the RSRC reg should be 256-bit, or the r128 flag is required");
+ else
+ Error(Loc, "operands are not valid for this GPU or mode");
+ return false;
+ }
+ return true;
+}
+
bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
const unsigned Opc = Inst.getOpcode();
@@ -5191,6 +5250,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
"invalid dim; must be MSAA type");
return false;
}
+ if (!validateMIMGR128(Inst, Operands))
+ return false;
+
if (!validateMIMGDataSize(Inst, IDLoc)) {
return false;
}
@@ -9786,13 +9848,6 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
case MCK_SReg_256:
case MCK_SReg_512:
return Operand.isNull() ? Match_Success : Match_InvalidOperand;
- case MCK_SReg_RSRC: {
- if (Operand.isReg())
- if (Operand.isRegClass(SReg_128_XNULLRegClassID) ||
- Operand.isRegClass(SReg_256_XNULLRegClassID))
- return Match_Success;
- return Match_InvalidOperand;
- }
default:
return Match_InvalidOperand;
}
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
index 172a4766256ca..b674fcd0d2780 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
@@ -42,9 +42,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D slc
image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
; GFX10: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x00,0xf0,0xff,0x00,0x00,0x80]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
-; GFX10: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
+image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+; GFX10: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x01,0x00,0xf0,0xff,0x00,0x00,0x00]
image_load v0, v[2:3], s[0:7] dmask:0x1 dim:2D
; GFX10: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
index f6ea86ed7fe93..820c4236be25c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
@@ -486,3 +486,33 @@ image_sample_o v[5:6], v[1:2], null, s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
image_sample_o v[5:6], v[1:2], s[8:15], null dmask:0x3 dim:SQ_RSRC_IMG_1D
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+
+image_atomic_add v5, v1, s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+
+image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D r128
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+
+image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+
+image_store v[0:3], v[254:255], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D r128
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+
+image_store v[0:3], v[254:255], s[12:15] dmask:0xf dim:SQ_RSRC_IMG_2D
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+
+image_sample v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+
+image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
index 1c8c7cf6823f2..43b724e6a2de9 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
@@ -39,9 +39,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D slc
image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16
// GFX11: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
-// GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
+image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x01,0x00,0xf0,0xff,0x00,0x00,0x00]
image_load v0, v[2:3], s[0:7] dmask:0x1 dim:2D
// GFX11: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
index 1f91e3b955eba..c5c5cb7d33cab 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
@@ -111,9 +111,8 @@ image_load v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
// GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
-image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
-// GFX12: encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX12: encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
// GFX12: encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -154,9 +153,8 @@ image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_LOAD_BYPASS scope:S
image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16
// GFX12: encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
-image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16
-// GFX12: encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
+image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16
+// GFX12: encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D
// GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00]
@@ -374,9 +372,8 @@ image_store v[1:4], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D
image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe
// GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
-image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
-// GFX12: encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
+// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D scope:SCOPE_CU
// GFX12: encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -558,9 +555,8 @@ image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCA
image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS
// GFX12: encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit RSRC.
-image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
-// GFX12: encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX12: encoding: [0x01,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16
// GFX12: encoding: [0x40,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vsample.s b/llvm/test/MC/AMDGPU/gfx12_asm_vsample.s
index bb036332e4b5a..2b7fa0af48015 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vsample.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vsample.s
@@ -39,9 +39,8 @@ image_sample v[16:19], [v20, v21], s[20:27], s[80:83] dmask:0xf dim:SQ_RSRC_IMG_
image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm
// GFX12: encoding: [0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128
-// GFX12: encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
+image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D
+// GFX12: encoding: [0x00,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
// GFX12: encoding: [0x01,0xc0,0x46,0xe4,0x1a,0x38,0x00,0x24,0x1b,0x1c,0x00,0x00]
@@ -94,9 +93,8 @@ image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe
// GFX12: encoding: [0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16
-// GFX12: encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
+image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV a16 tfe lwe d16
+// GFX12: encoding: [0x6b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
// GFX12: encoding: [0x00,0x00,0x47,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
@@ -461,9 +459,8 @@ image_gather4 v[64:67], [v32, v33], s[4:11], s[4:7] dmask:0x4 dim:SQ_RSRC_IMG_2D
image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm
// GFX12: encoding: [0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128
-// GFX12: encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
+image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D
+// GFX12: encoding: [0x01,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D scope:SCOPE_CU
// GFX12: encoding: [0x01,0xc0,0x8b,0xe4,0x0c,0x20,0x00,0x2e,0x10,0x11,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
index d9600fd638c19..3fbca5d81674d 100644
--- a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
@@ -1341,8 +1341,8 @@ image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 r128
-// CHECK: [0x00,0x81,0x5c,0xf0,0x01,0x05,0x02,0x00]
+image_atomic_umax v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf0,0x01,0x05,0x02,0x00]
image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/mimg-err.s b/llvm/test/MC/AMDGPU/mimg-err.s
index bec33bab984ab..641a7f4246483 100644
--- a/llvm/test/MC/AMDGPU/mimg-err.s
+++ b/llvm/test/MC/AMDGPU/mimg-err.s
@@ -98,3 +98,57 @@ image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
// NOGCN: error: invalid image_gather dmask: only one bit must be set
// NOGFX9: error: invalid image_gather dmask: only one bit must be set
// NOGFX90A: :[[@LINE-3]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+//===----------------------------------------------------------------------===//
+// R128
+//===----------------------------------------------------------------------===//
+
+image_atomic_add v5, v1, s[8:11] dmask:0x1
+// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX90A: error: operands are not valid for this GPU or mode
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 r128
+// NOGCN: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: error: r128 modifier is not supported on this GPU
+// NOGFX90A: error: r128 modifier is not supported on this GPU
+
+image_sample v[193:195], v[237:240], s[28:31], s[4:7] dmask:0x3
+// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX90A: error: operands are not valid for this GPU or mode
+
+image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x3 r128
+// NOGCN: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: error: r128 modifier is not supported on this GPU
+// NOGFX90A: error: r128 modifier is not supported on this GPU
+
+image_gather4 v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x3
+// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX90A: error: instruction not supported on this GPU
+
+image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3 r128
+// NOGCN: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: error: r128 modifier is not supported on this GPU
+// NOGFX90A: error: instruction not supported on this GPU
+
+image_load v[5:6], v1, s[8:11] dmask:0x1
+// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX90A: error: operands are not valid for this GPU or mode
+
+image_load v[5:6], v1, s[8:15] dmask:0x1 r128
+// NOGCN: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: error: r128 modifier is not supported on this GPU
+// NOGFX90A: error: r128 modifier is not supported on this GPU
+
+image_store v[4:7], v[237:240], s[28:31] dmask:0x7
+// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX9: error: operands are not valid for this GPU or mode
+// NOGFX90A: error: operands are not valid for this GPU or mode
+
+image_store v[4:7], v[237:240], s[28:35] dmask:0x7 r128
+// NOGCN: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: error: r128 modifier is not supported on this GPU
+// NOGFX90A: error: r128 modifier is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/mimg.s b/llvm/test/MC/AMDGPU/mimg.s
index 54bb2b19b2e84..bd6885f6eb287 100644
--- a/llvm/test/MC/AMDGPU/mimg.s
+++ b/llvm/test/MC/AMDGPU/mimg.s
@@ -1,7 +1,7 @@
-// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
-// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=SICIVI
-// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_0
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICIVI --check-prefix=VI --check-prefix=GFX89 --check-prefix=GFX8_1
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
+// RUN: not llvm-mc -triple=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX89 --check-prefix=GFX8_0
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx810 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX89 --check-prefix=GFX8_1
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX9 --check-prefix=GFX89
// RUN: not llvm-mc -triple=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
@@ -33,10 +33,9 @@ image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe
// GCN: image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
// Verify support of all possible modifiers.
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: d16 modifier is not supported on this GPU
-// VI: image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
image_load v5, v[1:4], s[8:15] d16
@@ -44,8 +43,9 @@ image_load v5, v[1:4], s[8:15] d16
// GFX89: image_load v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x80]
image_load v5, v[1:4], s[8:15] r128
-// SICIVI: image_load v5, v[1:4], s[8:15] r128 ; encoding: [0x00,0x80,0x00,0xf0,0x01,0x05,0x02,0x00]
-// NOGFX9: :[[@LINE-2]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
+// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
// GCN: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
@@ -66,20 +66,19 @@ image_store v[193:194], v[237:240], s[28:35] tfe
// GCN: image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
// Verify support of all possible modifiers.
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: d16 modifier is not supported on this GPU
-// VI: image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16 ; encoding: [0x00,0xf1,0x22,0xf2,0x01,0x05,0x02,0x80]
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
image_store v5, v[1:4], s[8:15] d16
// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: d16 modifier is not supported on this GPU
// GFX89: image_store v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x20,0xf0,0x01,0x05,0x02,0x80]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
image_store v5, v[1:4], s[8:15] r128
-// SICIVI: image_store v5, v[1:4], s[8:15] r128 ; encoding: [0x00,0x80,0x20,0xf0,0x01,0x05,0x02,0x00]
-// NOGFX9: :[[@LINE-2]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
+// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
//===----------------------------------------------------------------------===//
// Image Load/Store: d16 unpacked
@@ -324,10 +323,10 @@ image_sample v193, v[237:240], s[28:35], s[4:7]
image_sample v[193:194], v[237:240], s[28:35], s[4:7] tfe
// GCN: image_sample v[193:194], v[237:240], s[28:35], s[4:7] tfe ; encoding: [0x00,0x00,0x81,0xf0,0xed,0xc1,0x27,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
image_sample v193, v[237:240], s[28:35], s[4:7] r128
-// SICIVI: image_sample v193, v[237:240], s[28:35], s[4:7] r128 ; encoding: [0x00,0x80,0x80,0xf0,0xed,0xc1,0x27,0x00]
-// NOGFX9: :[[@LINE-2]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
+// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
image_sample v193, v[237:240], s[28:35], s[4:7] d16
// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: d16 modifier is not supported on this GPU
@@ -566,10 +565,9 @@ image_atomic_cmpswap v[4:8], v[192:195], s[28:35] dmask:0xf tfe
// SICI: image_atomic_cmpswap v[4:8], v[192:195], s[28:35] dmask:0xf tfe ; encoding: [0x00,0x0f,0x41,0xf0,0xc0,0x04,0x07,0x00]
// GFX89: image_atomic_cmpswap v[4:8], v[192:195], s[28:35] dmask:0xf tfe ; encoding: [0x00,0x0f,0x45,0xf0,0xc0,0x04,0x07,0x00]
-// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
image_atomic_add v10, v6, s[8:15] dmask:0x1 r128
-// SICI: image_atomic_add v10, v6, s[8:15] dmask:0x1 r128 ; encoding: [0x00,0x81,0x44,0xf0,0x06,0x0a,0x02,0x00]
-// VI: image_atomic_add v10, v6, s[8:15] dmask:0x1 r128 ; encoding: [0x00,0x81,0x48,0xf0,0x06,0x0a,0x02,0x00]
+// NOSICI: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
+// NOVI: :[[@LINE-2]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
// NOGFX9: :[[@LINE-3]]:{{[0-9]+}}: error: r128 modifier is not supported on this GPU
//===----------------------------------------------------------------------===//
>From 218f4e7224bf009fd54862d92c1cbf0863bbd61e Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Thu, 8 May 2025 08:45:59 -0700
Subject: [PATCH 7/9] Fix some tests after code update from main.
---
.../coalesce-copy-to-agpr-to-av-registers.mir | 148 +++++++++---------
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll | 24 +--
...al-regcopy-and-spill-missed-at-regalloc.ll | 32 ++--
.../CodeGen/AMDGPU/spill-vector-superclass.ll | 6 +-
.../Inputs/amdgpu_isel.ll.expected | 20 +--
5 files changed, 115 insertions(+), 115 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
index 69c0463d7d430..44b2a0d01a3d0 100644
--- a/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
+++ b/llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
@@ -533,13 +533,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -558,13 +558,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -585,7 +585,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -593,7 +593,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0.sub0
%3.sub1:areg_96 = COPY %0.sub1
%3.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -614,7 +614,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -622,7 +622,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0.sub0
%3.sub1:areg_96_align2 = COPY %0.sub1
%3.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -641,13 +641,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128 =COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -668,13 +668,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_128 =COPY $vgpr0_vgpr1
%0.sub1:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0.sub0
%2.sub2_sub3:areg_128_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -693,13 +693,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:sreg_64 = COPY $sgpr8
%0.sub1:sreg_64 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -718,13 +718,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub0
%2.sub1_sub2:areg_96 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -743,13 +743,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 =COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0.sub0
%2.sub1_sub2:areg_96_align2 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -768,13 +768,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0.sub0_sub1
%2.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -793,13 +793,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -817,12 +817,12 @@ body: |
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -841,13 +841,13 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_96 = COPY %0.sub0
%1.sub1:areg_96 = COPY %0.sub0
%1.sub2:areg_96 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %1
SI_RETURN
...
@@ -865,12 +865,12 @@ body: |
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_96_align2 = COPY %0.sub0
%1.sub1:areg_96_align2 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %1
SI_RETURN
...
@@ -890,14 +890,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_128 = COPY %0.sub0
%1.sub1:areg_128 = COPY %0.sub0
%1.sub2:areg_128 = COPY %0.sub0
%1.sub3:areg_128 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %1
SI_RETURN
...
@@ -917,14 +917,14 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_128_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub3:areg_128_align2 = COPY [[COPY]].sub0
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
undef %1.sub0:areg_128_align2 = COPY %0.sub0
%1.sub1:areg_128_align2 = COPY %0.sub0
%1.sub2:areg_128_align2 = COPY %0.sub0
%1.sub3:areg_128_align2 = COPY %0.sub0
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %1
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %1
SI_RETURN
...
@@ -943,13 +943,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64 = COPY $vgpr0
%0.sub1:vreg_64 = COPY $vgpr1
undef %2.sub0:areg_64 = COPY %0.sub0
%2.sub1:areg_64 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -968,13 +968,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:vreg_64_align2 = COPY $vgpr1
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_64_align2 = COPY $vgpr0
%0.sub1:vreg_64_align2 = COPY $vgpr1
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -995,7 +995,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1:vreg_96 = COPY $vgpr1
@@ -1003,7 +1003,7 @@ body: |
undef %3.sub0:areg_96 = COPY %0.sub0
%3.sub1:areg_96 = COPY %0.sub1
%3.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -1024,7 +1024,7 @@ body: |
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_96_align2 = COPY [[COPY]].sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96_align2 = COPY $vgpr0
%0.sub1:vreg_96_align2 = COPY $vgpr1
@@ -1032,7 +1032,7 @@ body: |
undef %3.sub0:areg_96_align2 = COPY %0.sub0
%3.sub1:areg_96_align2 = COPY %0.sub1
%3.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -1051,13 +1051,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128 = COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -1076,13 +1076,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2_sub3:vreg_128_align2 = COPY $vgpr2_vgpr3
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_128_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2_sub3:areg_128_align2 = COPY [[COPY]].sub2_sub3
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_128_align2 = COPY $vgpr0_vgpr1
%0.sub2_sub3:vreg_128_align2 = COPY $vgpr2_vgpr3
undef %2.sub0_sub1:areg_128_align2 = COPY %0.sub0_sub1
%2.sub2_sub3:areg_128_align2 = COPY %0.sub2_sub3
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -1101,13 +1101,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1:sreg_64 = COPY $sgpr9
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_64_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1:areg_64_align2 = COPY [[COPY]].sub1
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:sreg_64 = COPY $sgpr8
%0.sub1:sreg_64 = COPY $sgpr9
undef %2.sub0:areg_64_align2 = COPY %0.sub0
%2.sub1:areg_64_align2 = COPY %0.sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1126,13 +1126,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub0
%2.sub1_sub2:areg_96 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1150,13 +1150,13 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:areg_96 = COPY [[COPY]]
; CHECK-NEXT: [[COPY2:%[0-9]+]].sub1_sub2:areg_96 = COPY [[COPY1]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY2]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY2]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96 = COPY $vgpr0
%0.sub1_sub2:vreg_96 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96 = COPY %0.sub2
%2.sub1_sub2:areg_96 = COPY %0.sub0_sub1
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1176,13 +1176,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub1_sub2:vreg_96_align2 = COPY $vgpr1_vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0:areg_96_align2 = COPY [[COPY]].sub0
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub1_sub2:areg_96_align2 = COPY [[COPY]].sub1_sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0:vreg_96_align2 = COPY $vgpr0
%0.sub1_sub2:vreg_96_align2 = COPY $vgpr1_vgpr2
undef %2.sub0:areg_96_align2 = COPY %0.sub0
%2.sub1_sub2:areg_96_align2 = COPY %0.sub1_sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1201,13 +1201,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96 = COPY %0.sub0_sub1
%2.sub2:areg_96 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %2
SI_RETURN
...
@@ -1226,13 +1226,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96_align2 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96_align2 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96_align2 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1251,13 +1251,13 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]].sub2:vreg_96 = COPY $vgpr2
; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub0_sub1:areg_96_align2 = COPY [[COPY]].sub0_sub1
; CHECK-NEXT: [[COPY1:%[0-9]+]].sub2:areg_96_align2 = COPY [[COPY]].sub2
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
undef %0.sub0_sub1:vreg_96 = COPY $vgpr0_vgpr1
%0.sub2:vreg_96 = COPY $vgpr2
undef %2.sub0_sub1:areg_96_align2 = COPY %0.sub0_sub1
%2.sub2:areg_96_align2 = COPY %0.sub2
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1274,11 +1274,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64 = COPY $vgpr0_vgpr1
%2:areg_64 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3473417 /* reguse:AReg_64 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4456457 /* reguse:AReg_64 */, killed %2
SI_RETURN
...
@@ -1295,11 +1295,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_64_align2 = COPY $vgpr0_vgpr1
%2:areg_64_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1316,11 +1316,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
%3:areg_96 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 4587529 /* reguse:AReg_96 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5570569 /* reguse:AReg_96 */, %3
SI_RETURN
...
@@ -1337,11 +1337,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96_align2 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96_align2 = COPY $vgpr0_vgpr1_vgpr2
%3:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 4915209 /* reguse:AReg_96_Align2 */, %3
+ INLINEASM &"; use $0", 0 /* attdialect */, 5898249 /* reguse:AReg_96_Align2 */, %3
SI_RETURN
...
@@ -1358,11 +1358,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_128 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%2:areg_128 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 6029321 /* reguse:AReg_128 */, killed %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7012361 /* reguse:AReg_128 */, killed %2
SI_RETURN
...
@@ -1379,11 +1379,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_128_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_128_align2 = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%2:areg_128_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 6291465 /* reguse:AReg_128_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 7274505 /* reguse:AReg_128_Align2 */, %2
SI_RETURN
...
@@ -1400,11 +1400,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_64_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:sreg_64 = COPY $sgpr8_sgpr9
%2:areg_64_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
@@ -1421,11 +1421,11 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:areg_96_align2 = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, [[COPY1]]
; CHECK-NEXT: SI_RETURN
%0:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
%2:areg_96_align2 = COPY %0
- INLINEASM &"; use $0", 0 /* attdialect */, 3735561 /* reguse:AReg_64_Align2 */, %2
+ INLINEASM &"; use $0", 0 /* attdialect */, 4718601 /* reguse:AReg_64_Align2 */, %2
SI_RETURN
...
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
index b15f9e5a33646..4c378bd9ec280 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
@@ -8,15 +8,15 @@
define amdgpu_kernel void @s_input_output_i128() {
; GFX908-LABEL: name: s_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %12
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %13
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %13
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8192009 /* reguse:SGPR_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: s_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %10
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 8192010 /* regdef:SGPR_128 */, def %11
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %11
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 8192009 /* reguse:SGPR_128 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=s"()
@@ -27,15 +27,15 @@ define amdgpu_kernel void @s_input_output_i128() {
define amdgpu_kernel void @v_input_output_i128() {
; GFX908-LABEL: name: v_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %12
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %13
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %13
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7077897 /* reguse:VReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: v_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %10
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %11
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %11
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:VReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = tail call i128 asm sideeffect "; def $0", "=v"()
@@ -46,15 +46,15 @@ define amdgpu_kernel void @v_input_output_i128() {
define amdgpu_kernel void @a_input_output_i128() {
; GFX908-LABEL: name: a_input_output_i128
; GFX908: bb.0 (%ir-block.0):
- ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:AReg_128 */, def %12
- ; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %12
+ ; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:AReg_128 */, def %13
+ ; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %13
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7012361 /* reguse:AReg_128 */, [[COPY]]
; GFX908-NEXT: S_ENDPGM 0
;
; GFX90A-LABEL: name: a_input_output_i128
; GFX90A: bb.0 (%ir-block.0):
- ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7274506 /* regdef:AReg_128_Align2 */, def %10
- ; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %10
+ ; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7274506 /* regdef:AReg_128_Align2 */, def %11
+ ; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %11
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7274505 /* reguse:AReg_128_Align2 */, [[COPY]]
; GFX90A-NEXT: S_ENDPGM 0
%val = call i128 asm sideeffect "; def $0", "=a"()
diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
index 1e432a341b647..50b3357f4ecbb 100644
--- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
+++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
@@ -10,10 +10,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX908: bb.0 (%ir-block.0):
; REGALLOC-GFX908-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX908-NEXT: {{ $}}
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %5:agpr_32
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %6
- ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_64 */, def %7
- ; REGALLOC-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef %14:vreg_64, %6, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %6:agpr_32
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def %7
+ ; REGALLOC-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_64 */, def %8
+ ; REGALLOC-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64, %7, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; REGALLOC-GFX908-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
; REGALLOC-GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY killed renamable $sgpr0_sgpr1_sgpr2_sgpr3
; REGALLOC-GFX908-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
@@ -28,14 +28,14 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX908: bb.0 (%ir-block.0):
; PEI-GFX908-NEXT: liveins: $agpr4, $sgpr4_sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9
; PEI-GFX908-NEXT: {{ $}}
- ; PEI-GFX908-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
- ; PEI-GFX908-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $sgpr7, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
- ; PEI-GFX908-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX908-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; PEI-GFX908-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
+ ; PEI-GFX908-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
; PEI-GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef renamable $agpr0
; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7077898 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX908-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4521994 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1
- ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
+ ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
; PEI-GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1
; PEI-GFX908-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3, implicit $exec
; PEI-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
@@ -55,10 +55,10 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; REGALLOC-GFX90A: bb.0 (%ir-block.0):
; REGALLOC-GFX90A-NEXT: liveins: $sgpr4_sgpr5
; REGALLOC-GFX90A-NEXT: {{ $}}
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %5:agpr_32
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %6
- ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_64_Align2 */, def %7
- ; REGALLOC-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef %14:vreg_64_align2, %6, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef %6:agpr_32
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def %7
+ ; REGALLOC-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_64_Align2 */, def %8
+ ; REGALLOC-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef %15:vreg_64_align2, %7, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; REGALLOC-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
; REGALLOC-GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY killed renamable $sgpr0_sgpr1_sgpr2_sgpr3
; REGALLOC-GFX90A-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
@@ -72,14 +72,14 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 {
; PEI-GFX90A: bb.0 (%ir-block.0):
; PEI-GFX90A-NEXT: liveins: $agpr4, $sgpr4_sgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9
; PEI-GFX90A-NEXT: {{ $}}
- ; PEI-GFX90A-NEXT: $sgpr8_sgpr9_sgpr10_sgpr11 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
- ; PEI-GFX90A-NEXT: $sgpr8 = S_ADD_U32 $sgpr8, $sgpr7, implicit-def $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
- ; PEI-GFX90A-NEXT: $sgpr9 = S_ADDC_U32 $sgpr9, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
+ ; PEI-GFX90A-NEXT: $sgpr12_sgpr13_sgpr14_sgpr15 = COPY killed $sgpr0_sgpr1_sgpr2_sgpr3
+ ; PEI-GFX90A-NEXT: $sgpr12 = S_ADD_U32 $sgpr12, $sgpr9, implicit-def $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
+ ; PEI-GFX90A-NEXT: $sgpr13 = S_ADDC_U32 $sgpr13, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
; PEI-GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3145737 /* reguse:AGPR_32 */, undef renamable $agpr0
; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:VReg_128_Align2 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3
; PEI-GFX90A-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec
; PEI-GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 4849674 /* regdef:VReg_64_Align2 */, def renamable $vgpr0_vgpr1
- ; PEI-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
+ ; PEI-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5)
; PEI-GFX90A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1
; PEI-GFX90A-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $agpr0_agpr1_agpr2_agpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
; PEI-GFX90A-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = S_LOAD_DWORDX4_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (s128) from %ir.arg.kernarg.offset1, addrspace 4)
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
index 7dc0a92c906f6..e4add15445ab2 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
@@ -12,10 +12,10 @@ define amdgpu_kernel void @test_spill_av_class(<4 x i32> %arg) #0 {
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
; GCN-NEXT: [[V_MFMA_I32_4X4X4I8_e64_:%[0-9]+]]:areg_128 = V_MFMA_I32_4X4X4I8_e64 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], [[COPY]], 0, 0, 0, implicit $mode, implicit $exec
- ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3211274 /* regdef:VGPR_32 */, def undef %13.sub0
+ ; GCN-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 3211274 /* regdef:VGPR_32 */, def undef %14.sub0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY [[V_MFMA_I32_4X4X4I8_e64_]]
- ; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %23:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
- ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4521993 /* reguse:VReg_64 */, %13
+ ; GCN-NEXT: GLOBAL_STORE_DWORDX4 undef %24:vreg_64, [[COPY1]], 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1)
+ ; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4521993 /* reguse:VReg_64 */, %14
; GCN-NEXT: S_ENDPGM 0
%v0 = call i32 asm sideeffect "; def $0", "=v"()
%tmp = insertelement <2 x i32> poison, i32 %v0, i32 0
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
index 925622148a561..f515ee651d835 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
@@ -7,16 +7,16 @@ define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8
; CHECK-NEXT: t4: i32,ch = CopyFromReg # D:1 t0, Register:i32 %9
-; CHECK-NEXT: t49: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11>
-; CHECK-NEXT: t26: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
-; CHECK-NEXT: t29: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
-; CHECK-NEXT: t32: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t26, TargetConstant:i32<3>, t29, TargetConstant:i32<11>
-; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t49, t32
-; CHECK-NEXT: t23: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3>
-; CHECK-NEXT: t16: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t23
-; CHECK-NEXT: t38: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11>
-; CHECK-NEXT: t18: ch,glue = CopyToReg # D:1 t16, Register:i32 $vgpr1, t38, t16:1
-; CHECK-NEXT: t19: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t18, t18:1
+; CHECK-NEXT: t50: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11>
+; CHECK-NEXT: t27: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
+; CHECK-NEXT: t30: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
+; CHECK-NEXT: t33: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<75>, t27, TargetConstant:i32<3>, t30, TargetConstant:i32<11>
+; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t50, t33
+; CHECK-NEXT: t24: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3>
+; CHECK-NEXT: t17: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t24
+; CHECK-NEXT: t39: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11>
+; CHECK-NEXT: t19: ch,glue = CopyToReg # D:1 t17, Register:i32 $vgpr1, t39, t17:1
+; CHECK-NEXT: t20: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t19, t19:1
; CHECK-EMPTY:
%loc = alloca i64, addrspace(5)
%j = load i64, ptr addrspace(5) %loc
>From cc05ff1a0099737e4286b45544c4ff86547aa0a1 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Mon, 19 May 2025 16:28:06 -0700
Subject: [PATCH 8/9] Fix disassembler
---
.../Disassembler/AMDGPUDisassembler.cpp | 14 +++++++++
.../MC/Disassembler/AMDGPU/gfx10_mimg.txt | 31 +++++++++++++++++--
.../AMDGPU/gfx11_dasm_mimg_features.txt | 24 +++++++++++++-
.../Disassembler/AMDGPU/gfx12_dasm_vimage.txt | 8 ++---
.../AMDGPU/gfx12_dasm_vimage_features.txt | 23 ++++++++++++++
.../AMDGPU/gfx12_dasm_vsample.txt | 9 ++----
.../AMDGPU/gfx8_mimg_features.txt | 17 ++++++++--
.../MC/Disassembler/AMDGPU/gfx90a_mimg.txt | 7 +++++
.../AMDGPU/gfx9_mimg_features.txt | 3 ++
9 files changed, 120 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index c0786252c4849..0af807f950f7c 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1207,6 +1207,20 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
}
}
+ // Update RSRC reg to 128b if r128 flag is present.
+ int R128Idx =
+ AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::r128);
+ if (AMDGPU::hasMIMG_R128(STI) && R128Idx != -1 &&
+ MI.getOperand(R128Idx).getImm()) {
+ // Get first subregister of RSRC
+ MCRegister RsrcReg = MI.getOperand(RsrcIdx).getReg();
+ MCRegister RsrcSubReg0 = MRI.getSubReg(RsrcReg, AMDGPU::sub0);
+ MCRegister NewRsrcReg = MRI.getMatchingSuperReg(
+ RsrcSubReg0, AMDGPU::sub0,
+ &MRI.getRegClass(AMDGPU::SReg_128_XNULLRegClassID));
+ MI.getOperand(RsrcIdx) = MCOperand::createReg(NewRsrcReg);
+ }
+
unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1);
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
index 39f94e39c4cb9..0c999b59175a6 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
@@ -43,8 +43,7 @@
# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm dlc ; encoding: [0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00]
0x88,0x1f,0x14,0xf0,0x08,0x10,0x01,0x00
-# TODO: This is incorrect: r128 should use a 128-bit register for srsrc
-# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
+# GFX10: image_load_mip_pck_sgn v[16:19], v[8:10], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00]
0x08,0x9f,0x14,0xf0,0x08,0x10,0x01,0x00
# GFX10: image_load v16, v[8:9], s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x01,0x00,0xf0,0x08,0x10,0x18,0x00]
@@ -305,6 +304,19 @@
# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm lwe ; encoding: [0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00]
0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00
+# r128
+# GFX10: image_load v[252:255], v[2:4], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_3D unorm r128 ; encoding: [0x10,0x9f,0x00,0xf0,0x02,0xfc,0x00,0x00]
+0x10,0x9f,0x00,0xf0,0x02,0xfc,0x00,0x00
+
+# GFX10: image_store v16, v[8:9], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x08,0x81,0x20,0xf0,0x08,0x10,0x18,0x00]
+0x08,0x81,0x20,0xf0,0x08,0x10,0x18,0x00
+
+# GFX10: image_sample_o v[16:19], v[252:255], s[20:23], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY r128 ; encoding: [0x28,0x8f,0xc0,0xf0,0xfc,0x10,0x25,0x03]
+0x28,0x8f,0xc0,0xf0,0xfc,0x10,0x25,0x03
+
+# GFX10: image_atomic_swap v16, v8, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm r128 ; encoding: [0x00,0x91,0x3c,0xf0,0x08,0x10,0x18,0x00]
+0x00,0x91,0x3c,0xf0,0x08,0x10,0x18,0x00
+
#===------------------------------------------------------------------------===#
# MIMG, NSA address
#===------------------------------------------------------------------------===#
@@ -548,6 +560,19 @@
# GFX10: image_sample_c_cd_cl_o v[16:19], [v8, v9, v10, v11, v12, v13, v14], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; encoding: [0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x00,0x00]
0x24,0x0f,0xbc,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10
+# r128
+# GFX10: image_atomic_cmpswap v[16:17], [v8, v9], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x0a,0x83,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00]
+0x0a,0x83,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00
+
+# GFX10: image_gather4 v[16:19], [v8, v9, v10], s[20:23], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x81,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
+0x12,0x81,0x00,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00
+
+# GFX10: image_atomic_umax v16, [v8, v9, v10, v11], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY r128 ; encoding: [0x3a,0x81,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x00]
+0x3a,0x81,0x5c,0xf0,0x08,0x10,0x18,0x00,0x09,0x0a,0x0b,0x00
+
+# GFX10: image_get_lod v[16:19], [v8, v9, v10], s[20:23], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x8f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
+0x12,0x8f,0x80,0xf1,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00
+
#===------------------------------------------------------------------------===#
# MIMG, Miscellaneous instructions
#===------------------------------------------------------------------------===#
@@ -579,7 +604,7 @@
# GFX10: image_store_mip v1, v[2:3], s[12:19] dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x24,0xf0,0x02,0x01,0x03,0x00]
0x00,0x00,0x24,0xf0,0x02,0x01,0x03,0x00
-# GFX10: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+# GFX10: image_store_mip_pck v252, v[2:3], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]
0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00
# GFX10: image_atomic_sub v4, v192, s[28:35] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0xc0,0x04,0x07,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
index e28325f986ea3..c721c1f61e69e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt
@@ -39,7 +39,7 @@
# GFX11: image_load v0, v255, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; encoding: [0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00]
0x00,0x06,0x02,0xf0,0xff,0x00,0x00,0x00
-# GFX11: image_load v0, v255, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
+# GFX11: image_load v0, v255, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00]
0x00,0x81,0x00,0xf0,0xff,0x00,0x00,0x00
# GFX11: image_load v0, v[2:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x04,0x01,0x00,0xf0,0x02,0x00,0x00,0x00]
@@ -217,6 +217,28 @@
# GFX11: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
0x00,0x03,0x50,0xf0,0x01,0x05,0x22,0x00
+#===------------------------------------------------------------------------===#
+# r128
+#===------------------------------------------------------------------------===#
+
+# GFX11: image_load v[1:4], [v2, v3], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x85,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00,0x03,0x00,0x00,0x00]
+0x85,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00,0x03,0x00,0x00,0x00
+
+# GFX11: image_load v[1:4], v[2:3], s[4:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm r128 ; encoding: [0x84,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00]
+0x84,0x8f,0x00,0xf0,0x02,0x01,0x01,0x00
+
+# GFX11: image_store v[0:3], v[254:255], s[96:99] dmask:0xf dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x04,0x8f,0x18,0xf0,0xfe,0x00,0x18,0x00]
+0x04,0x8f,0x18,0xf0,0xfe,0x00,0x18,0x00
+
+# GFX11: image_get_resinfo v[4:7], v32, s[96:99] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x08,0x8f,0x5c,0xf0,0x20,0x04,0x18,0x00]
+0x08,0x8f,0x5c,0xf0,0x20,0x04,0x18,0x00
+
+# GFX11: image_atomic_cmpswap v[4:5], [v32, v1, v2], s[96:99] dmask:0x3 dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x09,0x83,0x2c,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00]
+0x09,0x83,0x2c,0xf0,0x20,0x04,0x18,0x00,0x01,0x02,0x00,0x00
+
+# GFX11: image_gather4 v[64:67], v32, s[4:7], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x00,0x81,0xbc,0xf0,0x20,0x40,0x01,0x64]
+0x00,0x81,0xbc,0xf0,0x20,0x40,0x01,0x64
+
# GFX11: image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64]
0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
index 85fbd82543c5f..4a62ce144d3b8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
@@ -108,7 +108,7 @@
# GFX12: image_load v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
0x01,0x00,0xc0,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00
-# GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+# GFX12: image_load v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
0x10,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
# GFX12: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x40,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -154,7 +154,7 @@
# GFX12: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE a16 tfe d16 ; encoding: [0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
0x65,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00
-# GFX12: image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16 ; encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
+# GFX12: image_load v[0:2], [v4, v5], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LOAD_HT scope:SCOPE_SE r128 a16 tfe d16 ; encoding: [0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00]
0x75,0x00,0xc0,0xd3,0x00,0x10,0xa4,0x00,0x04,0x05,0x00,0x00
# GFX12: image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00]
@@ -370,7 +370,7 @@
# GFX12: image_store v[1:5], [v0, v1], s[16:23] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; encoding: [0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00]
0x01,0x80,0xc1,0xd3,0x01,0x20,0x80,0x00,0x00,0x01,0x00,0x00
-# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+# GFX12: image_store v0, v0, s[0:3] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
0x10,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
# GFX12: image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x80,0x41,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
@@ -550,7 +550,7 @@
# GFX12: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_CASCADE_NT scope:SCOPE_SYS ; encoding: [0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00]
0x00,0x80,0x42,0xd0,0x00,0x00,0x6c,0x00,0x00,0x00,0x00,0x00
-# GFX12: image_atomic_swap v0, [v2, v3], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
+# GFX12: image_atomic_swap v0, [v2, v3], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00]
0x11,0x80,0x42,0xd0,0x00,0x08,0x00,0x00,0x02,0x03,0x00,0x00
# GFX12: image_atomic_swap v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x40,0x80,0x42,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt
index 2e747adbd0720..50d08f5bd1e75 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt
@@ -99,3 +99,26 @@
# GFX12: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
0x00,0x00,0xc5,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
+
+#===------------------------------------------------------------------------===#
+# r128
+#===------------------------------------------------------------------------===#
+
+# GFX12: image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+0x10,0x00,0xc0,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+
+# GFX12: image_load v[4:7], [v4, v5, v6], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D r128 ; encoding: [0x12,0x00,0xc0,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+0x12,0x00,0xc0,0xd3,0x04,0x10,0x00,0x00,0x04,0x05,0x06,0x00
+
+# GFX12: image_store v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00]
+0x10,0x80,0xc1,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+
+# GFX12: image_get_resinfo v4, v32, s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00]
+0x10,0xc0,0x45,0xd0,0x04,0xc0,0x00,0x00,0x20,0x00,0x00,0x00
+
+# GFX12: image_atomic_swap v[1:2], [v4, v5, v6], s[8:11] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY r128 ; encoding: [0x15,0x80,0xc2,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00]
+0x15,0x80,0xc2,0xd0,0x01,0x10,0x00,0x00,0x04,0x05,0x06,0x00
+
+# GFX12: image_atomic_swap v2, v4, s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0x80,0x42,0xd0,0x02,0x10,0x00,0x00,0x04,0x00,0x00,0x00]
+0x10,0x80,0x42,0xd0,0x02,0x10,0x00,0x00,0x04,0x00,0x00,0x00
+
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
index 99824cc692dd0..090d1ba76ea9d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vsample.txt
@@ -39,8 +39,7 @@
# GFX12: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
0x00,0xe0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00
-# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-# GFX12: image_sample v[22:24], v25, s[24:31], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
+# GFX12: image_sample v[22:24], v25, s[24:27], s[76:79] dmask:0xd dim:SQ_RSRC_IMG_1D r128 ; encoding: [0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00]
0x10,0xc0,0x46,0xe7,0x16,0x30,0x00,0x26,0x19,0x00,0x00,0x00
# GFX12: image_sample v26, [v27, v28], s[28:35], s[72:75] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x46,0xe4,0x1a,0x38,0x00,0x24,0x1b,0x1c,0x00,0x00]
@@ -94,8 +93,7 @@
# GFX12: image_sample v[34:35], v37, s[36:43], s[64:67] dmask:0x3 dim:SQ_RSRC_IMG_1D lwe ; encoding: [0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00]
0x00,0xc0,0xc6,0xe4,0x22,0x49,0x00,0x20,0x25,0x00,0x00,0x00
-# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-# GFX12: image_sample v[38:39], [v40, v41], s[40:47], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16 ; encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
+# GFX12: image_sample v[38:39], [v40, v41], s[40:43], s[60:63] dmask:0xc dim:SQ_RSRC_IMG_CUBE unorm th:TH_LOAD_HT scope:SCOPE_DEV r128 a16 tfe lwe d16 ; encoding: [0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00]
0x7b,0xe0,0x06,0xe7,0x26,0x51,0x28,0x1e,0x28,0x29,0x00,0x00
# GFX12: image_sample_d v64, [v32, v33, v34], s[4:11], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x00,0x47,0xe4,0x40,0x08,0x00,0x02,0x20,0x21,0x22,0x00]
@@ -461,8 +459,7 @@
# GFX12: image_gather4 v[0:3], [v4, v5], s[0:7], s[100:103] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00]
0x01,0xe0,0x0b,0xe6,0x00,0x00,0x00,0x32,0x04,0x05,0x00,0x00
-# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-# GFX12: image_gather4 v[6:9], [v10, v11], s[8:15], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
+# GFX12: image_gather4 v[6:9], [v10, v11], s[8:11], s[96:99] dmask:0x1 dim:SQ_RSRC_IMG_2D r128 ; encoding: [0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00]
0x11,0xc0,0x4b,0xe4,0x06,0x10,0x00,0x30,0x0a,0x0b,0x00,0x00
# GFX12: image_gather4 v[12:15], [v16, v17], s[16:23], s[92:95] dmask:0x2 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0xc0,0x8b,0xe4,0x0c,0x20,0x00,0x2e,0x10,0x11,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
index 67153515b64bb..afb1e0119d80a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt
@@ -30,8 +30,9 @@
0x00 0x11 0x20 0xf0 0x01 0x00 0x00 0x00
# Test all modifiers
-# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
-# VI: image_load v[5:6], v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
+
+# Test r128
+# VI: image_load v[5:6], v1, s[8:11] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80
# Test dmask == 0
@@ -48,6 +49,9 @@
# VI: image_load v255, v0, s[0:7] dmask:0x3 unorm ; encoding: [0x00,0x13,0x00,0xf0,0x00,0xff,0x00,0x00]
0x00 0x13 0x00 0xf0 0x00 0xff 0x00 0x00
+# VI: image_store v[0:1], v2, s[0:3] dmask:0x3 unorm r128 ; encoding: [0x00,0x93,0x20,0xf0,0x02,0x00,0x00,0x00]
+0x00,0x93,0x20,0xf0,0x02,0x00,0x00,0x00
+
#===------------------------------------------------------------------------===#
# Image load/store: packed/unpacked d16
#===------------------------------------------------------------------------===#
@@ -147,6 +151,9 @@
# GFX81: image_sample v[193:194], v237, s[28:35], s[4:7] dmask:0xf d16 ; encoding: [0x00,0x0f,0x80,0xf0,0xed,0xc1,0x27,0x80]
0x00,0x0f,0x80,0xf0,0xed,0xc1,0x27,0x80
+# VI: image_sample v[193:195], v237, s[28:31], s[4:7] dmask:0x7 unorm r128 ; encoding: [0x00,0x97,0x80,0xf0,0xed,0xc1,0x27,0x00]
+0x00,0x97,0x80,0xf0,0xed,0xc1,0x27,0x00
+
#===------------------------------------------------------------------------===#
# Image atomics
#===------------------------------------------------------------------------===#
@@ -178,12 +185,18 @@
# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00
+# VI: image_atomic_add v5, v1, s[8:11] dmask:0x1 unorm r128 ; encoding: [0x00,0x91,0x48,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x91,0x48,0xf0,0x01,0x05,0x02,0x00
+
# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm ; encoding: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00
# VI: image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00
+# VI: image_atomic_cmpswap v[5:8], v1, s[8:11] dmask:0xf unorm r128 ; encoding: [0x00,0x9f,0x44,0xf0,0x01,0x05,0x02,0x00]
+0x00,0x9f,0x44,0xf0,0x01,0x05,0x02,0x00
+
# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 tfe
0x00,0x01,0x49,0xf0,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
index 0f2dca4cb5783..b62042dbaa780 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_mimg.txt
@@ -74,3 +74,10 @@
0x00,0x01,0x80,0xf0,0x00,0x05,0x62,0x00
# GFX90A: image_sample v5, v0, s[8:15], s[12:15] dmask:0x1 ; encoding: [0x00,0x01,0x80,0xf0,0x00,0x05,0x62,0x00]
+
+# Rsrc reg is 256b regardless of a16
+# GFX90A: image_sample v6, v0, s[8:15], s[12:15] dmask:0x1 a16 ; encoding: [0x00,0x81,0x80,0xf0,0x00,0x06,0x62,0x00]
+0x00,0x81,0x80,0xf0,0x00,0x06,0x62,0x00
+
+# GFX90A: image_sample v[6:7], v0, s[8:15], s[12:15] dmask:0x3 a16 ; encoding: [0x00,0x83,0x80,0xf0,0x00,0x06,0x62,0x00]
+0x00,0x83,0x80,0xf0,0x00,0x06,0x62,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt
index 8300fe4e9db50..d82946f0a1df0 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt
@@ -81,3 +81,6 @@
# GFX900: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 tfe
0x00,0x03,0x69,0xf0,0x01,0x05,0x02,0x00
+# Rsrc reg size is 256b regardless of a16
+# GFX900: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x3 a16
+0x00,0x83,0x68,0xf0,0x01,0x05,0x02,0x00
>From 59bfdb4521940805dc7e013fdcb4cc51229f14a2 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 20 May 2025 10:58:36 -0700
Subject: [PATCH 9/9] some minor changes
---
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 6 ++++--
llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s | 10 +++++-----
llvm/test/MC/AMDGPU/mimg-err.s | 10 +++++-----
3 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9596fe3709a44..2bb691008f803 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4021,11 +4021,13 @@ bool AMDGPUAsmParser::validateMIMGR128(const MCInst &Inst,
auto Loc = getImmLoc(AMDGPUOperand::ImmTyR128A16, Operands);
Error(Loc, "r128 not allowed with 256-bit RSRC reg");
return false;
- } else if (SrsrcRegSize == 4 && !IsR128) {
+ }
+
+ if (SrsrcRegSize == 4 && !IsR128) {
auto Loc = getInstLoc(Operands);
if (hasMIMG_R128())
Error(Loc,
- "the RSRC reg should be 256-bit, or the r128 flag is required");
+ "rsrc reg should be 256-bit, or the r128 flag is required");
else
Error(Loc, "operands are not valid for this GPU or mode");
return false;
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
index 820c4236be25c..d7f51d30d8e0c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg_err.s
@@ -491,28 +491,28 @@ image_atomic_add v5, v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
image_atomic_add v5, v1, s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: rsrc reg should be 256-bit, or the r128 flag is required
image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D r128
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
image_load v[0:3], v0, s[0:3] dmask:0xf dim:SQ_RSRC_IMG_1D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: rsrc reg should be 256-bit, or the r128 flag is required
image_store v[0:3], v[254:255], s[12:19] dmask:0xf dim:SQ_RSRC_IMG_2D r128
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
image_store v[0:3], v[254:255], s[12:15] dmask:0xf dim:SQ_RSRC_IMG_2D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: rsrc reg should be 256-bit, or the r128 flag is required
image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D r128
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
image_sample v[5:6], v1, s[8:11], s[12:15] dmask:0x3 dim:SQ_RSRC_IMG_1D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: rsrc reg should be 256-bit, or the r128 flag is required
image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D r128
// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: r128 not allowed with 256-bit RSRC reg
image_gather4 v[5:8], v[1:2], s[8:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_1D
-// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGFX10: :[[@LINE-1]]:{{[0-9]+}}: error: rsrc reg should be 256-bit, or the r128 flag is required
diff --git a/llvm/test/MC/AMDGPU/mimg-err.s b/llvm/test/MC/AMDGPU/mimg-err.s
index 641a7f4246483..b012c94da59ca 100644
--- a/llvm/test/MC/AMDGPU/mimg-err.s
+++ b/llvm/test/MC/AMDGPU/mimg-err.s
@@ -104,7 +104,7 @@ image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3
//===----------------------------------------------------------------------===//
image_atomic_add v5, v1, s[8:11] dmask:0x1
-// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGCN: error: rsrc reg should be 256-bit, or the r128 flag is required
// NOGFX9: error: operands are not valid for this GPU or mode
// NOGFX90A: error: operands are not valid for this GPU or mode
@@ -114,7 +114,7 @@ image_atomic_add v5, v1, s[8:15] dmask:0x1 r128
// NOGFX90A: error: r128 modifier is not supported on this GPU
image_sample v[193:195], v[237:240], s[28:31], s[4:7] dmask:0x3
-// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGCN: error: rsrc reg should be 256-bit, or the r128 flag is required
// NOGFX9: error: operands are not valid for this GPU or mode
// NOGFX90A: error: operands are not valid for this GPU or mode
@@ -124,7 +124,7 @@ image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x3 r128
// NOGFX90A: error: r128 modifier is not supported on this GPU
image_gather4 v[5:8], v[1:4], s[8:11], s[12:15] dmask:0x3
-// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGCN: error: rsrc reg should be 256-bit, or the r128 flag is required
// NOGFX9: error: operands are not valid for this GPU or mode
// NOGFX90A: error: instruction not supported on this GPU
@@ -134,7 +134,7 @@ image_gather4 v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x3 r128
// NOGFX90A: error: instruction not supported on this GPU
image_load v[5:6], v1, s[8:11] dmask:0x1
-// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGCN: error: rsrc reg should be 256-bit, or the r128 flag is required
// NOGFX9: error: operands are not valid for this GPU or mode
// NOGFX90A: error: operands are not valid for this GPU or mode
@@ -144,7 +144,7 @@ image_load v[5:6], v1, s[8:15] dmask:0x1 r128
// NOGFX90A: error: r128 modifier is not supported on this GPU
image_store v[4:7], v[237:240], s[28:31] dmask:0x7
-// NOGCN: error: the RSRC reg should be 256-bit, or the r128 flag is required
+// NOGCN: error: rsrc reg should be 256-bit, or the r128 flag is required
// NOGFX9: error: operands are not valid for this GPU or mode
// NOGFX90A: error: operands are not valid for this GPU or mode
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