[llvm] [RISCV] Add scheduling model for SiFive P800 processors (PR #139316)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/18637

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
32.464 [2126/40/1714] Linking CXX static library lib/libLLVMSystemZDisassembler.a
32.508 [2126/39/1715] Building RISCVGenSearchableTables.inc...
32.517 [2126/38/1716] Building X86GenAsmWriter.inc...
32.834 [2126/37/1717] Building X86GenAsmWriter1.inc...
32.861 [2126/36/1718] Building X86GenRegisterBank.inc...
32.876 [2126/35/1719] Building CXX object lib/Target/SystemZ/AsmParser/CMakeFiles/LLVMSystemZAsmParser.dir/SystemZAsmParser.cpp.o
32.985 [2126/34/1720] Building X86GenRegisterInfo.inc...
33.037 [2126/33/1721] Building X86GenDisassemblerTables.inc...
33.406 [2126/32/1722] Building X86GenAsmMatcher.inc...
33.537 [2126/31/1723] Building RISCVGenSubtargetInfo.inc...
FAILED: lib/Target/RISCV/RISCVGenSubtargetInfo.inc /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 
cd /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-tblgen -gen-subtarget -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include -I /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o RISCVGenSubtargetInfo.inc -d RISCVGenSubtargetInfo.inc.d && /usr/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /b/ml-opt-rel-x86-64-b1/llvm-project/llvm /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV /b/ml-opt-rel-x86-64-b1/build /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV /b/ml-opt-rel-x86-64-b1/build/lib/Target/RISCV/RISCVGenSubtargetInfo.inc.d /b/ml-opt-rel-x86-64-b1/build/CMakeFiles/d/528c4a0a29196eeadf7af497fd38a8c95b469e50aa5e0b9eeba29e508cc2c496.d
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:61:
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td:61:5: error: Processor does not define resources for WriteFAdd128
def SiFiveP800Model : SchedMachineModel {
    ^
33.949 [2126/30/1724] Building X86GenInstrMapping.inc...
33.965 [2126/29/1725] Building X86GenMnemonicTables.inc...
34.880 [2126/28/1726] Building X86GenFoldTables.inc...
37.025 [2126/27/1727] Building CXX object lib/MC/MCParser/CMakeFiles/LLVMMCParser.dir/AsmParser.cpp.o
37.952 [2126/26/1728] Building X86GenFastISel.inc...
39.080 [2126/25/1729] Building X86GenGlobalISel.inc...
41.355 [2126/24/1730] Building X86GenDAGISel.inc...
41.415 [2126/23/1731] Building AArch64GenSubtargetInfo.inc...
41.487 [2126/22/1732] Building X86GenSubtargetInfo.inc...
42.869 [2126/21/1733] Building AArch64GenInstrInfo.inc...
44.839 [2126/20/1734] Building AMDGPUGenRegBankGICombiner.inc...
44.844 [2126/19/1735] Building AMDGPUGenPreLegalizeGICombiner.inc...
45.973 [2126/18/1736] Building AMDGPUGenMCPseudoLowering.inc...
46.453 [2126/17/1737] Building X86GenInstrInfo.inc...
47.735 [2126/16/1738] Building AMDGPUGenPostLegalizeGICombiner.inc...
48.257 [2126/15/1739] Building RISCVGenInstrInfo.inc...
48.526 [2126/14/1740] Building RISCVGenGlobalISel.inc...
48.737 [2126/13/1741] Building AMDGPUGenMCCodeEmitter.inc...
49.013 [2126/12/1742] Building AMDGPUGenCallingConv.inc...
49.024 [2126/11/1743] Building AMDGPUGenSubtargetInfo.inc...
49.034 [2126/10/1744] Building AMDGPUGenDisassemblerTables.inc...
49.802 [2126/9/1745] Building AMDGPUGenSearchableTables.inc...
51.940 [2126/8/1746] Building AMDGPUGenAsmWriter.inc...
52.416 [2126/7/1747] Building RISCVGenDAGISel.inc...
53.028 [2126/6/1748] Building AMDGPUGenGlobalISel.inc...
55.210 [2126/5/1749] Building AMDGPUGenAsmMatcher.inc...
56.927 [2126/4/1750] Building AMDGPUGenDAGISel.inc...
58.391 [2126/3/1751] Building AMDGPUGenInstrInfo.inc...
58.863 [2126/2/1752] Building AMDGPUGenRegisterBank.inc...
61.082 [2126/1/1753] Building AMDGPUGenRegisterInfo.inc...
ninja: build stopped: subcommand failed.

```

</details>

https://github.com/llvm/llvm-project/pull/139316