[llvm] b3c3297 - [RISCV] Fix missing WriteRes for Q extensions in SiFiveP800 scheudling model

[Min-Yih Hsu via llvm-commits]

Author: Min-Yih Hsu
Date: 2025-05-20T09:24:48-07:00
New Revision: b3c3297c1a8ee85efac7236b47883bc0b89d1883

URL: https://github.com/llvm/llvm-project/commit/b3c3297c1a8ee85efac7236b47883bc0b89d1883
DIFF: https://github.com/llvm/llvm-project/commit/b3c3297c1a8ee85efac7236b47883bc0b89d1883.diff

LOG: [RISCV] Fix missing WriteRes for Q extensions in SiFiveP800 scheudling model

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index c14c8888f6d55..f2b660583f27f 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -1176,10 +1176,12 @@ foreach mx = SchedMxList in {
 
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
+defm : UnsupportedSchedQ;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedXsfvcp;
 }