[llvm] 4a0ae4f - [RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo. (#140640)

[via llvm-commits]

Author: Craig Topper
Date: 2025-05-20T09:01:03-07:00
New Revision: 4a0ae4f504c82869355349dd22b89f2228b886f3

URL: https://github.com/llvm/llvm-project/commit/4a0ae4f504c82869355349dd22b89f2228b886f3
DIFF: https://github.com/llvm/llvm-project/commit/4a0ae4f504c82869355349dd22b89f2228b886f3.diff

LOG: [RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo. (#140640)

isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth

The first 2 probably requires spills/reloads which we don't use
LD_RV32/SD_RV32 for yet.

I think getMemOperandsWithOffsetWidth is mainly used for load/store
clustering. I think we can assume this just works.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 2f152305e2ae0..590b45172d43c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -156,6 +156,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -206,6 +207,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -3057,8 +3059,10 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
   case RISCV::SW_INX:
   case RISCV::FSW:
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     break;
   default: