[llvm] [AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (PR #140062)

[Kerry McLaughlin via llvm-commits]

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@@ -6595,6 +6617,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_REVERSE(SDNode *N) {
                               Mask);
 }
 
+SDValue DAGTypeLegalizer::WidenVecRes_GET_ACTIVE_LANE_MASK(SDNode *N) {
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+  return DAG.getNode(ISD::GET_ACTIVE_LANE_MASK, SDLoc(N), NVT, N->ops());
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kmclaughlin-arm wrote:

It is the `@lane_mask_nxv7i1_i64` test which triggers the widening code. From what I understand and from trying out a few other examples, the widened vector is treated as a number of contigous vectors.
In the example you gave we will generate one <vscale x 8 x i1> get_active_lane_mask which is interpreted as contiguous when extracting element 7, i.e.:

```
whilelo  p0.h, x0, x1
mov   z0.h, p0/z, #1    // =0x1
umov  w8, v0.h[7]
and   w0, w8, #0x1
ret
```

https://github.com/llvm/llvm-project/pull/140062