[llvm] [AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (PR #140062)

[Kerry McLaughlin via llvm-commits]

================
@@ -930,8 +930,8 @@ define void @get_lane_mask() #0 {
 ; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of 16 for: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef)
 ; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of 8 for: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef)
 ; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of 4 for: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef)
-; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of RThru:48 CodeSize:33 Lat:33 SizeLat:33 for: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef)
-; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of RThru:6 CodeSize:5 Lat:5 SizeLat:5 for: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
+; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of 64 for: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef)
+; CHECK-VSCALE-1-NEXT:  Cost Model: Found costs of 32 for: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef)
----------------
kmclaughlin-arm wrote:

This is coming from `AArch64TTIImpl::getIntrinsicInstrCost`, which returns a high cost for fixed-vector types which are not legal even if `shouldExpandGetActiveLaneMask` returns false:

```
if (!getTLI()->shouldExpandGetActiveLaneMask(RetVT, OpVT) &&
    !getTLI()->isTypeLegal(RetVT)) {
    // We don't have enough context at this point to determine if the mask
    // is going to be kept live after the block, which will force the vXi1
    // type to be expanded to legal vectors of integers, e.g. v4i1->v4i32.
    // For now, we just assume the vectorizer created this intrinsic and
    // the result will be the input for a PHI. In this case the cost will
    // be extremely high for fixed-width vectors.
```

https://github.com/llvm/llvm-project/pull/140062