[llvm] [RISCV] Add Xqcibi Select_GPR_Using_CC_<Imm> Pseudos to isSelectPseudo (PR #140698)
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Tue May 20 02:49:02 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sudharsan Veeravalli (svs-quic)
<details>
<summary>Changes</summary>
Not adding them was leading to a crash when trying to expand these pseudo instructions.
I've also fixed the register class types for the Xqcibi instructions in these pseudo instructions which was incorrect and was exposed by the machine verifier while running the test case added in this patch.
Fixes #<!-- -->140697
---
Full diff: https://github.com/llvm/llvm-project/pull/140698.diff
6 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+5-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+4-4)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+8-8)
- (modified) llvm/lib/Target/RISCV/RISCVInstrPredicates.td (+4)
- (modified) llvm/test/CodeGen/RISCV/xqcibi.ll (+27)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1158499718737..5f9e3f2080683 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21018,7 +21018,11 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
- MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5) &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5 &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm5NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm16NonZero &&
+ MI.getOpcode() != RISCV::Select_GPR_Using_CC_UImm16NonZero) &&
Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
Next->getOperand(5).isKill())
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 41b3a57315b57..84b1e639cee35 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1646,12 +1646,12 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
def : SelectCompressOpt<SETNE>;
}
-multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
+multiclass SelectCC_GPR_riirr<DAGOperand outvalty, DAGOperand invalty, DAGOperand imm> {
let usesCustomInserter = 1 in
def Select_GPR_Using_ # NAME
- : Pseudo<(outs valty:$dst),
- (ins GPR:$lhs, imm:$imm, cond_code:$cc,
- valty:$truev, valty:$falsev), []>;
+ : Pseudo<(outs outvalty:$dst),
+ (ins invalty:$lhs, imm:$imm, cond_code:$cc,
+ outvalty:$truev, outvalty:$falsev), []>;
}
/// Branches and jumps
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 2b068e66bcf21..f735e2b3e57c0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -802,7 +802,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
- defm CC_SImm5 : SelectCC_GPR_riirr<GPR, simm5>;
+ defm CC_SImm5 : SelectCC_GPR_riirr<GPR, GPR, simm5>;
class Selectbi<CondCode Cond>
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 04db0fd07f109..4ac952ef121b2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1327,16 +1327,16 @@ class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
-defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPR, simm5nonzero>;
-defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPR, uimm5nonzero>;
-defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPR, simm16nonzero>;
-defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPR, uimm16nonzero>;
+defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm5nonzero>;
+defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm5nonzero>;
+defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, simm16nonzero>;
+defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPRNoX0, GPRNoX0, uimm16nonzero>;
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
- : Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
- (i32 GPR:$truev), GPR:$falsev),
- (OpNode GPR:$lhs, InTyImm:$Constant,
- (IntCCtoQCRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
+ : Pat<(riscv_selectcc_frag:$cc (i32 GPRNoX0:$lhs), InTyImm:$Constant, Cond,
+ (i32 GPRNoX0:$truev), GPRNoX0:$falsev),
+ (OpNode GPRNoX0:$lhs, InTyImm:$Constant,
+ (IntCCtoQCRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;
/// Simple arithmetic operations
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 5056f6f5baf4d..d8b1a5d8dc14a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -50,6 +50,10 @@ def isSelectPseudo
CheckOpcode<[
Select_GPR_Using_CC_GPR,
Select_GPR_Using_CC_SImm5,
+ Select_GPR_Using_CC_SImm5NonZero,
+ Select_GPR_Using_CC_UImm5NonZero,
+ Select_GPR_Using_CC_SImm16NonZero,
+ Select_GPR_Using_CC_UImm16NonZero,
Select_FPR16_Using_CC_GPR,
Select_FPR16INX_Using_CC_GPR,
Select_FPR32_Using_CC_GPR,
diff --git a/llvm/test/CodeGen/RISCV/xqcibi.ll b/llvm/test/CodeGen/RISCV/xqcibi.ll
index 242012b5ad462..f628e0086374c 100644
--- a/llvm/test/CodeGen/RISCV/xqcibi.ll
+++ b/llvm/test/CodeGen/RISCV/xqcibi.ll
@@ -355,5 +355,32 @@ t:
ret i32 1
}
+define i1 @selectcc(i64 %0) {
+; RV32I-LABEL: selectcc:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: li a2, 512
+; RV32I-NEXT: beq a1, a2, .LBB12_2
+; RV32I-NEXT: # %bb.1: # %entry
+; RV32I-NEXT: sltiu a0, a1, 513
+; RV32I-NEXT: xori a0, a0, 1
+; RV32I-NEXT: ret
+; RV32I-NEXT: .LBB12_2:
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: ret
+;
+; RV32IXQCIBI-LABEL: selectcc:
+; RV32IXQCIBI: # %bb.0: # %entry
+; RV32IXQCIBI-NEXT: qc.e.beqi a1, 512, .LBB12_2
+; RV32IXQCIBI-NEXT: # %bb.1: # %entry
+; RV32IXQCIBI-NEXT: sltiu a0, a1, 513
+; RV32IXQCIBI-NEXT: xori a0, a0, 1
+; RV32IXQCIBI-NEXT: ret
+; RV32IXQCIBI-NEXT: .LBB12_2:
+; RV32IXQCIBI-NEXT: snez a0, a0
+; RV32IXQCIBI-NEXT: ret
+entry:
+ %cmp10.i = icmp ugt i64 %0, 2199023255552
+ ret i1 %cmp10.i
+}
!0 = !{!"branch_weights", i32 1, i32 99}
``````````
</details>
https://github.com/llvm/llvm-project/pull/140698
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