[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 6f0c524d3..7381a34de 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -235,7 +235,6 @@ bool VectorLegalizer::Run() {
 
   LegalizedNodes.clear();
 
-
   // Remove dead nodes now.
   DAG.RemoveDeadNodes();
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 388efe036..7ed055e8d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -152,7 +152,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::LOAD, MVT::i128, Promote);
   AddPromotedToType(ISD::LOAD, MVT::i128, MVT::v4i32);
-  
+
   // TODO: Would be better to consume as directly legal
   setOperationAction(ISD::ATOMIC_LOAD, MVT::f32, Promote);
   AddPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 7338abd67..fa8692135 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -432,9 +432,11 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, MVT::v2i32, Legal);
-  // Prevent SELECT from being implemented with the above bitwise ops and instead use cndmask.
+  // Prevent SELECT from being implemented with the above bitwise ops and
+  // instead use cndmask.
   setOperationAction(ISD::SELECT, MVT::v2i32, Custom);
- // Enable MatchRotate to produce ISD::ROTR, which is later transformed to alignbit.
+  // Enable MatchRotate to produce ISD::ROTR, which is later transformed to
+  // alignbit.
   setOperationAction(ISD::ROTR, MVT::v2i32, Legal);
 
   setOperationAction(ISD::BUILD_VECTOR, {MVT::v4f16, MVT::v4i16, MVT::v4bf16},
@@ -12898,9 +12900,8 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
       SDValue CLHS = LHS->getOperand(1);
       SDValue CRHS = RHS->getOperand(0);
       SDValue BVRHS = RHS->getOperand(1);
-      LLVM_DEBUG(
-          dbgs()
-              << "### Performing v2i32 SIISelLowering DAGCombine::CombineOR\n";);
+      LLVM_DEBUG(dbgs() << "### Performing v2i32 SIISelLowering "
+                           "DAGCombine::CombineOR\n";);
 
       auto *LC = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
       auto *RC = dyn_cast<ConstantSDNode>(RHS->getOperand(0));
@@ -12976,7 +12977,7 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
                                             DAGCombinerInfo &DCI) const {
   if (SDValue RV = reassociateScalarOps(N, DCI.DAG))
     return RV;
-  
+
   SelectionDAG &DAG = DCI.DAG;
   EVT VT = N->getValueType(0);
   SDValue LHS = N->getOperand(0);
@@ -13009,19 +13010,17 @@ SDValue SITargetLowering::performXorCombine(SDNode *N,
     // Possibly split vector here if one side does have a constant RHS.
   }
 
-  // Add test for when only one of the RHS vector elements is a const. Might be possible to optimise this case.
-
+  // Add test for when only one of the RHS vector elements is a const. Might be
+  // possible to optimise this case.
 
   const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
- 
- 
+
   if (CRHS && VT == MVT::i64) {
     if (SDValue Split =
             splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
       return Split;
   }
 
-
   // Make sure to apply the 64-bit constant splitting fold before trying to fold
   // fneg-like xors into 64-bit select.
   if (LHS.getOpcode() == ISD::SELECT && VT == MVT::i32) {

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https://github.com/llvm/llvm-project/pull/140694