[llvm] b95ad8e - [DAGCombine] Use isLegalExtLoad for MatchLoadCombine (#140536)

[via llvm-commits]

Author: David Green
Date: 2025-05-20T09:59:41+01:00
New Revision: b95ad8eca6ae1ef73b4ee3018b69446995f39353

URL: https://github.com/llvm/llvm-project/commit/b95ad8eca6ae1ef73b4ee3018b69446995f39353
DIFF: https://github.com/llvm/llvm-project/commit/b95ad8eca6ae1ef73b4ee3018b69446995f39353.diff

LOG: [DAGCombine] Use isLegalExtLoad for MatchLoadCombine (#140536)

This looks wrong to me, but I don't have a test case where it alters the
generated code.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 68693cef06ee6..531f6fb2a627a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9482,8 +9482,8 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
   // split into legal sized loads. This enables us to combine i64 load by i8
   // patterns to a couple of i32 loads on 32 bit targets.
   if (LegalOperations &&
-      !TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD,
-                            MemVT))
+      !TLI.isLoadExtLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, VT,
+                          MemVT))
     return SDValue();
 
   // Check if the bytes of the OR we are looking at match with either big or