[llvm] [LoongArch] Introduce `32s` target feature for LA32S ISA extensions (PR #139695)

[via llvm-commits]

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@@ -1447,10 +1471,49 @@ def : Pat<(setle GPR:$rj, GPR:$rk), (XORI (SLT GPR:$rk, GPR:$rj), 1)>;
 
 /// Select
 
+def IntCCtoBranchOpc : SDNodeXForm<loongarch_selectcc, [{
+  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  unsigned BrCC = getBranchOpcForIntCC(CC);
+  return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getGRLenVT());
+}]>;
+
+def loongarch_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
+                                           node:$truev, node:$falsev),
+                                      (loongarch_selectcc node:$lhs, node:$rhs,
+                                                          node:$cc, node:$truev,
+                                                          node:$falsev), [{}],
+                                      IntCCtoBranchOpc>;
+
+multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {
+  let usesCustomInserter = 1 in
+  def _Using_CC_GPR : Pseudo<(outs valty:$dst),
+                             (ins GPR:$lhs, GPR:$rhs, GPR:$cc,
+                              valty:$truev, valty:$falsev),
+                             [(set valty:$dst,
+                               (loongarch_selectcc_frag:$cc (GRLenVT GPR:$lhs), GPR:$rhs, cond,
+                                                            (vt valty:$truev), valty:$falsev))]>;
+  // Explicitly select 0 in the condition to R0. The register coalescer doesn't
+  // always do it.
+  def : Pat<(loongarch_selectcc_frag:$cc (GRLenVT GPR:$lhs), 0, cond, (vt valty:$truev),
+                                         valty:$falsev),
+            (!cast<Instruction>(NAME#"_Using_CC_GPR") GPR:$lhs, (GRLenVT R0),
+             (IntCCtoBranchOpc $cc), valty:$truev, valty:$falsev)>;
+}
+
+defm Select_GPR : SelectCC_GPR_rrirr<GPR, GRLenVT>;
+
+class SelectCompressOpt<CondCode Cond>
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heiher wrote:

Yup :smiley: 

https://github.com/llvm/llvm-project/pull/139695