[llvm] RISCV, LoongArch: Encode RELAX relocation implicitly (PR #140494)

[Fangrui Song via llvm-commits]

MaskRay wrote:

> This is looking much better, and easier to extend than the previous structure, thanks.
> 
> I think there's still a bunch of complexity around forcing relocations in relax mode, for instance in the top of `RISCVAsmParser::parseInstruction` and equivalently in `RISCVTargetELFStreamer::RISCVTargetELFStreamer`, but maybe the work to mark a specific fragment needing relaxation can help simplify this.

I have just tested that the code in `RISCVTargetELFStreamer::RISCVTargetELFStreamer` (#77436) is still needed as the test case has a true `IsResolved`.
In MCAssembler.cpp, `getWriter().isSymbolRefDifferenceFullyResolvedImpl(` doesn't check whether `*Add, *DF` are separated by a relaxable instruction, and sets `IsResolved` to true.

https://github.com/llvm/llvm-project/pull/140494