[llvm] [RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo. (PR #140640)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/140640

isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth

The first 2 probably requires spills/reloads which we don't use LD_RV32/SD_RV32 for yet.

I think getMemOperandsWithOffsetWidth is mainly used for load/store clustering. I think we can assume this just works, but I can try to add a test if reviewers want.

>From 121f42a90228db23b0d9f86ae274b51d2b8f453f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 19 May 2025 15:35:21 -0700
Subject: [PATCH] [RISCV] Add LD_RV32/SD_RV32 to a few more functions in
 RISCVInstrInfo.

isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth

The first 2 probably requires spills/reloads which we don't use
LD_RV32/SD_RV32 for yet.

I think getMemOperandsWithOffsetWidth is mainly used for load/store
clustering.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e9e5fa8d8042a..6c6ccc2c6244d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -156,6 +156,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -206,6 +207,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -3055,8 +3057,10 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
   case RISCV::SW_INX:
   case RISCV::FSW:
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     break;
   default: