[llvm] [RISCV] Add LD_RV32/SD_RV32 to RISCVInstrInfo::canFoldIntoAddrMode. (PR #140631)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon May 19 14:50:00 PDT 2025
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/140631
None
>From 0f172f3686a73d8610a55a3a22102746e50b88e6 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 19 May 2025 14:27:34 -0700
Subject: [PATCH 1/2] Pre-commit test
---
.../RISCV/fold-addi-loadstore-zilsd.ll | 110 ++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
index e34c5272ebaeb..919c63bda1b07 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
@@ -28,3 +28,113 @@ entry:
store double 0.0, ptr @g_0
ret void
}
+
+%struct.S = type { double, double }
+
+define double @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind {
+; CHECK-LABEL: fold_addi_from_different_bb:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -48
+; CHECK-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
+; CHECK-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
+; CHECK-NEXT: mv s0, a4
+; CHECK-NEXT: mv s1, a3
+; CHECK-NEXT: mv s2, a2
+; CHECK-NEXT: beqz a3, .LBB2_3
+; CHECK-NEXT: # %bb.1: # %entry
+; CHECK-NEXT: slti a1, s1, 0
+; CHECK-NEXT: beqz a1, .LBB2_4
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: fcvt.d.w s4, zero
+; CHECK-NEXT: j .LBB2_6
+; CHECK-NEXT: .LBB2_3:
+; CHECK-NEXT: seqz a1, s2
+; CHECK-NEXT: bnez a1, .LBB2_2
+; CHECK-NEXT: .LBB2_4: # %for.body.lr.ph
+; CHECK-NEXT: li s3, 0
+; CHECK-NEXT: li s6, 0
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, s0, a0
+; CHECK-NEXT: addi s7, a0, 8
+; CHECK-NEXT: fcvt.d.w s4, zero
+; CHECK-NEXT: .LBB2_5: # %for.body
+; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: mv a0, s0
+; CHECK-NEXT: call f
+; CHECK-NEXT: ld a0, 0(s7)
+; CHECK-NEXT: addi s3, s3, 1
+; CHECK-NEXT: seqz a2, s3
+; CHECK-NEXT: add s6, s6, a2
+; CHECK-NEXT: xor a2, s3, s2
+; CHECK-NEXT: xor a3, s6, s1
+; CHECK-NEXT: or a2, a2, a3
+; CHECK-NEXT: fadd.d s4, a0, s4
+; CHECK-NEXT: bnez a2, .LBB2_5
+; CHECK-NEXT: .LBB2_6: # %for.cond.cleanup
+; CHECK-NEXT: mv a0, s4
+; CHECK-NEXT: mv a1, s5
+; CHECK-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
+; CHECK-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 48
+; CHECK-NEXT: ret
+entry:
+ %cmp4 = icmp sgt i64 %n, 0
+ br i1 %cmp4, label %for.body.lr.ph, label %for.cond.cleanup
+
+for.body.lr.ph: ; preds = %entry
+ %y = getelementptr inbounds %struct.S, ptr %a, i64 %k, i32 1
+ br label %for.body
+
+for.cond.cleanup: ; preds = %for.body, %entry
+ %s.0.lcssa = phi double [ 0.0, %entry ], [ %add, %for.body ]
+ ret double %s.0.lcssa
+
+for.body: ; preds = %for.body.lr.ph, %for.body
+ %i.06 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+ %s.05 = phi double [ 0.0, %for.body.lr.ph ], [ %add, %for.body ]
+ call void @f(ptr %a)
+ %0 = load double, ptr %y, align 8
+ %add = fadd double %0, %s.05
+ %inc = add nuw nsw i64 %i.06, 1
+ %exitcond.not = icmp eq i64 %inc, %n
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
+declare void @f(ptr)
+
+define void @split_offset(ptr %dest, double %x) {
+; CHECK-LABEL: split_offset:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: addi a0, a0, 2047
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: addi a1, a0, 1
+; CHECK-NEXT: sd a2, 1(a0)
+; CHECK-NEXT: sd a2, 8(a1)
+; CHECK-NEXT: sd a2, 16(a1)
+; CHECK-NEXT: sd a2, 24(a1)
+; CHECK-NEXT: ret
+ %p1 = getelementptr double, ptr %dest, i32 256
+ store double %x, ptr %p1
+ %p2 = getelementptr double, ptr %dest, i32 257
+ store double %x, ptr %p2
+ %p3 = getelementptr double, ptr %dest, i32 258
+ store double %x, ptr %p3
+ %p4 = getelementptr double, ptr %dest, i32 259
+ store double %x, ptr %p4
+ ret void
+}
>From c8806fac1ee243943958f1512bb752210fdcb860 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 19 May 2025 14:28:00 -0700
Subject: [PATCH 2/2] [RISCV] Add LD_RV32/SD_RV32 to
RISCVInstrInfo::canFoldIntoAddrMode.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 ++
llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll | 12 +++++-------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e9e5fa8d8042a..2f152305e2ae0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2935,6 +2935,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
case RISCV::LW_INX:
case RISCV::LWU:
case RISCV::LD:
+ case RISCV::LD_RV32:
case RISCV::FLH:
case RISCV::FLW:
case RISCV::FLD:
@@ -2944,6 +2945,7 @@ bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
case RISCV::SW:
case RISCV::SW_INX:
case RISCV::SD:
+ case RISCV::SD_RV32:
case RISCV::FSH:
case RISCV::FSW:
case RISCV::FSD:
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
index 919c63bda1b07..fce42cb7a46f7 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll
@@ -61,14 +61,13 @@ define double @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind {
; CHECK-NEXT: li s3, 0
; CHECK-NEXT: li s6, 0
; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, s0, a0
-; CHECK-NEXT: addi s7, a0, 8
+; CHECK-NEXT: add s7, s0, a0
; CHECK-NEXT: fcvt.d.w s4, zero
; CHECK-NEXT: .LBB2_5: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: call f
-; CHECK-NEXT: ld a0, 0(s7)
+; CHECK-NEXT: ld a0, 8(s7)
; CHECK-NEXT: addi s3, s3, 1
; CHECK-NEXT: seqz a2, s3
; CHECK-NEXT: add s6, s6, a2
@@ -122,11 +121,10 @@ define void @split_offset(ptr %dest, double %x) {
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: addi a0, a0, 2047
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: sd a2, 1(a0)
-; CHECK-NEXT: sd a2, 8(a1)
-; CHECK-NEXT: sd a2, 16(a1)
-; CHECK-NEXT: sd a2, 24(a1)
+; CHECK-NEXT: sd a2, 9(a0)
+; CHECK-NEXT: sd a2, 17(a0)
+; CHECK-NEXT: sd a2, 25(a0)
; CHECK-NEXT: ret
%p1 = getelementptr double, ptr %dest, i32 256
store double %x, ptr %p1
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