[llvm] [LLVM][AArch64]CFINV - Add UNPREDICTABLE behaviour if CRm is not zero (PR #140593)

via llvm-commits llvm-commits at lists.llvm.org
Mon May 19 11:42:43 PDT 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: None (CarolineConcatto)

<details>
<summary>Changes</summary>

Now CFINV follows AXFLAGS behaviour for CRm.

It looks like (0) in the instruction encoding means that the behaviour is UNPREDICTABLE if that bit is not zero.

---
Full diff: https://github.com/llvm/llvm-project/pull/140593.diff


3 Files Affected:

- (added) 0001-Add-FP8-ACLE-macros-implementation.patch (+160) 
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+1) 
- (modified) llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt (+2) 


``````````diff
diff --git a/0001-Add-FP8-ACLE-macros-implementation.patch b/0001-Add-FP8-ACLE-macros-implementation.patch
new file mode 100644
index 0000000000000..a73083fccca27
--- /dev/null
+++ b/0001-Add-FP8-ACLE-macros-implementation.patch
@@ -0,0 +1,160 @@
+From f31b5b2fa13f047ebef3f5a3dab35382379b8914 Mon Sep 17 00:00:00 2001
+From: CarolineConcatto <caroline.concatto at arm.com>
+Date: Mon, 19 May 2025 18:21:28 +0000
+Subject: [PATCH] Add FP8 ACLE macros implementation
+
+This patch implements the macros described in the ACLE[1]
+
+[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#modal-8-bit-floating-point-extensions
+---
+ clang/lib/Basic/Targets/AArch64.cpp           | 59 +++++++++++++++++++
+ clang/lib/Basic/Targets/AArch64.h             |  9 +++
+ .../Preprocessor/aarch64-target-features.c    | 31 ++++++++++
+ 3 files changed, 99 insertions(+)
+
+diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
+index e1f6c7b834dc..7267b17704a4 100644
+--- a/clang/lib/Basic/Targets/AArch64.cpp
++++ b/clang/lib/Basic/Targets/AArch64.cpp
+@@ -596,6 +596,33 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
+   if (HasSMEB16B16)
+     Builder.defineMacro("__ARM_FEATURE_SME_B16B16", "1");
+ 
++  if (HasFP8)
++    Builder.defineMacro("__ARM_FEATURE_FP8", "1");
++
++  if (HasFP8FMA)
++    Builder.defineMacro("__ARM_FEATURE_FP8FMA", "1");
++
++  if (HasFP8DOT2)
++    Builder.defineMacro("__ARM_FEATURE_FP8DOT2", "1");
++
++  if (HasFP8DOT4)
++    Builder.defineMacro("__ARM_FEATURE_FP8DOT4", "1");
++
++  if (HasSSVE_FP8DOT2)
++    Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT2", "1");
++
++  if (HasSSVE_FP8DOT4)
++    Builder.defineMacro("__ARM_FEATURE_SSVE_FP8DOT4", "1");
++
++  if (HasSSVE_FP8FMA)
++    Builder.defineMacro("__ARM_FEATURE_SSVE_FP8FMA", "1");
++
++  if (HasSME_F8F32)
++    Builder.defineMacro("__ARM_FEATURE_SME_F8F32", "1");
++
++  if (HasSME_F8F16)
++    Builder.defineMacro("__ARM_FEATURE_SME_F8F16", "1");
++
+   if (HasCRC)
+     Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
+ 
+@@ -885,6 +912,15 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const {
+       .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
+       .Case("wfxt", HasWFxT)
+       .Case("rcpc3", HasRCPC3)
++      .Case("fp8", HasFP8)
++      .Case("fp8fma", HasFP8FMA)
++      .Case("fp8dot2", HasFP8DOT2)
++      .Case("fp8dot4", HasFP8DOT4)
++      .Case("ssve-fp8dot2", HasSSVE_FP8DOT2)
++      .Case("ssve-fp8dot4", HasSSVE_FP8DOT4)
++      .Case("ssve-fp8fma", HasSSVE_FP8FMA)
++      .Case("sme-f8f32", HasSME_F8F32)
++      .Case("sme-f8f16", HasSME_F8F16)
+       .Default(false);
+ }
+ 
+@@ -1046,6 +1082,29 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
+       HasSVEB16B16 = true;
+       HasSMEB16B16 = true;
+     }
++
++    if (Feature == "+fp8")
++      HasFP8 = true;
++    if (Feature == "+fp8fma")
++      HasFP8FMA = true;
++    if (Feature == "+fp8dot2")
++      HasFP8DOT2 = true;
++    if (Feature == "+fp8dot4")
++      HasFP8DOT4 = true;
++    if (Feature == "+ssve-fp8dot2")
++      HasSSVE_FP8DOT2 = true;
++    if (Feature == "+ssve-fp8dot4")
++      HasSSVE_FP8DOT4 = true;
++    if (Feature == "+ssve-fp8fma")
++      HasSSVE_FP8FMA = true;
++    if (Feature == "+sme-f8f32") {
++      HasSME2 = true;
++      HasSME_F8F32 = true;
++    }
++    if (Feature == "+sme-f8f16") {
++      HasSME2 = true;
++      HasSME_F8F16 = true;
++    }
+     if (Feature == "+sb")
+       HasSB = true;
+     if (Feature == "+predres")
+diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h
+index 6eeac69af20d..7230f22d5bb8 100644
+--- a/clang/lib/Basic/Targets/AArch64.h
++++ b/clang/lib/Basic/Targets/AArch64.h
+@@ -106,6 +106,15 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
+   bool HasSMEF16F16 = false;
+   bool HasSMEB16B16 = false;
+   bool HasSME2p1 = false;
++  bool HasFP8 = false;
++  bool HasFP8FMA = false;
++  bool HasFP8DOT2 = false;
++  bool HasFP8DOT4 = false;
++  bool HasSSVE_FP8DOT2 = false;
++  bool HasSSVE_FP8DOT4 = false;
++  bool HasSSVE_FP8FMA = false;
++  bool HasSME_F8F32 = false;
++  bool HasSME_F8F16 = false;
+   bool HasSB = false;
+   bool HasPredRes = false;
+   bool HasSSBS = false;
+diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
+index 3f801c434494..52045d216262 100644
+--- a/clang/test/Preprocessor/aarch64-target-features.c
++++ b/clang/test/Preprocessor/aarch64-target-features.c
+@@ -744,3 +744,34 @@
+ // CHECK-SMEB16B16: __ARM_FEATURE_SME2 1
+ // CHECK-SMEB16B16: __ARM_FEATURE_SME_B16B16 1
+ // CHECK-SMEB16B16: __ARM_FEATURE_SVE_B16B16 1
++//
++//  RUN: %clang --target=aarch64 -march=armv9-a+fp8 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8 %s
++// CHECK-FP8: __ARM_FEATURE_FP8 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+fp8fma -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8FMA %s
++// CHECK-FP8FMA: __ARM_FEATURE_FP8FMA 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+fp8dot2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8DOT2 %s
++// CHECK-FP8DOT2: __ARM_FEATURE_FP8DOT2 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+fp8dot4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FP8DOT4 %s
++// CHECK-FP8DOT4: __ARM_FEATURE_FP8DOT4 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8dot2 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8DOT2 %s
++// CHECK-SSVE-FP8DOT2: __ARM_FEATURE_SSVE_FP8DOT2 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8dot4 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8DOT4 %s
++// CHECK-SSVE-FP8DOT4: __ARM_FEATURE_SSVE_FP8DOT4 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+ssve-fp8fma -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SSVE-FP8FMA %s
++// CHECK-SSVE-FP8FMA: __ARM_FEATURE_SSVE_FP8FMA 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+sme-f8f32 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SMEF8F32 %s
++// CHECK-SMEF8F32: __ARM_FEATURE_LOCALLY_STREAMING 1
++// CHECK-SMEF8F32: __ARM_FEATURE_SME2 1
++// CHECK-SMEF8F32: __ARM_FEATURE_SME_F8F32 1
++
++// RUN: %clang --target=aarch64 -march=armv9-a+sme-f8f16 -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SMEF8F16 %s
++// CHECK-SMEF8F16: __ARM_FEATURE_LOCALLY_STREAMING 1
++// CHECK-SMEF8F16: __ARM_FEATURE_SME2 1
++// CHECK-SMEF8F16: __ARM_FEATURE_SME_F8F16 1
+-- 
+2.43.0
+
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 010c7c391527f..22ecf99b12de6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2096,6 +2096,7 @@ def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
 let Predicates = [HasFlagM], Defs = [NZCV], Uses = [NZCV] in {
 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
   let Inst{20-5} = 0b0000001000000000;
+  let Unpredictable{11-8} = 0b1111;
 }
 def SETF8  : BaseFlagManipulation<0, 0, (ins GPR32:$Rn), "setf8", "{\t$Rn}">;
 def SETF16 : BaseFlagManipulation<0, 1, (ins GPR32:$Rn), "setf16", "{\t$Rn}">;
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt
index c29109d578f2c..1f12c2cca0de1 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-flag.txt
@@ -2,10 +2,12 @@
 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r --disassemble < %s | FileCheck %s
 
 [0x1f,0x40,0x00,0xd5]
+[0x1f,0x4f,0x00,0xd5]
 [0x2d,0x08,0x00,0x3a]
 [0x2d,0x48,0x00,0x3a]
 [0x2f,0x84,0x1f,0xba]
 
+#CHECK:  cfinv
 #CHECK:  cfinv
 #CHECK:  setf8  w1
 #CHECK:  setf16  w1

``````````

</details>


https://github.com/llvm/llvm-project/pull/140593


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