[llvm] [BOLT][AArch64] Add tests for unsupported conditional tailcalls (PR #139565)

[Paschalis Mpeis via llvm-commits]

paschalis-mpeis wrote:

Hey @maksfb ,

Sharing my thoughts to be sure we are aligned before I proceed with the below proposal.

The B or BL cases were simple because there was a 1-1 mapping between relocation types and instructions. We only needed a hardcoded opcode and the immediate value to patch (see BL example [here](https://github.com/llvm/llvm-project/blob/dbb79c30c9f3578b7afd9ea0ec33f82e70e472c7/bolt/lib/Core/Relocation.cpp#L306)).

Supporting conditional branches is slightly more involved. A single relocation type covers instructions that use the same number of bits for the immediate to be patched. So, `CONDBR19` applies to both B.cond and CBZ/CBNZ. We also need to preserve some bits that are 'somewhat dynamic'. For example, the register in a CBZ instruction, the condition-code bits in B.cond, and more.

My plan is to read the original instruction encoding from the BinarySection Contents during relocation flushing, and pass it as an extra parameter to `Relocation::encodeValue`. Then, when encoding the patched instruction, preserve any of these bits I mention above as needed by extracting them from the original encoding.

What do you think? I can post a draft patch if it's unclear.

(cc: @yota9)

https://github.com/llvm/llvm-project/pull/139565