[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Benjamin Maxwell via llvm-commits]

================
@@ -7340,15 +7289,6 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
     return cast<VTSDNode>(Root->getOperand(3))->getVT();
   case AArch64ISD::ST1_PRED:
     return cast<VTSDNode>(Root->getOperand(4))->getVT();
-  case AArch64ISD::SVE_LD2_MERGE_ZERO:
-    return getPackedVectorTypeFromPredicateType(
-        Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/2);
-  case AArch64ISD::SVE_LD3_MERGE_ZERO:
-    return getPackedVectorTypeFromPredicateType(
-        Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/3);
-  case AArch64ISD::SVE_LD4_MERGE_ZERO:
-    return getPackedVectorTypeFromPredicateType(
-        Ctx, Root->getOperand(1)->getValueType(0), /*NumVec=*/4);
----------------
MacDue wrote:

Are the `SVE_LD{2,3,4}_MERGE_ZERO` nodes intentionally unused (due to some refactor)? There's no code path that uses them currently (but it seems a little suspect). `INDEX_VECTOR` seems to have been intentionally removed (everywhere but the `AArch64ISD` enum).

https://github.com/llvm/llvm-project/pull/140472