[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Benjamin Maxwell via llvm-commits]

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@@ -1,12 +1,12 @@
-//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
+//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp ------------------===//
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MacDue wrote:

Replace the line :+1: (I have no strong feelings about splitting the `unittests/` changes off or not). 

https://github.com/llvm/llvm-project/pull/140472