[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Benjamin Maxwell via llvm-commits]

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@@ -23,22 +27,20 @@ static cl::opt<bool>
                                 "to lower to librt functions"),
                        cl::init(true));
 
-bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
-  return Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
-         Opcode <= AArch64ISD::LAST_MEMORY_OPCODE;
-}
-
-bool AArch64SelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
-  return Opcode >= AArch64ISD::FIRST_STRICTFP_OPCODE &&
-         Opcode <= AArch64ISD::LAST_STRICTFP_OPCODE;
-}
+AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(AArch64GenSDNodeInfo) {}
 
 void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
                                                const SDNode *N) const {
 #ifndef NDEBUG
   switch (N->getOpcode()) {
   default:
-    break;
+    return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
+  case AArch64ISD::SMSTART:
+  case AArch64ISD::SMSTOP:
+    // FIXME: These can't be verified by SelectionDAGGenTargetInfo as the
+    // variadic "PStateSM" operand is not a Register or RegisterMask.
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MacDue wrote:

Thanks for the suggestion (I was going to ask about this case), I've gone with splitting the node into `COND_` variants (that seems like the cleanest option) :+1:  

https://github.com/llvm/llvm-project/pull/140472