[llvm] [X86] matchBinaryPermuteShuffle - match AVX512 "cross lane" SHLDQ/SRLDQ style patterns using VALIGN (PR #140538)

via llvm-commits llvm-commits at lists.llvm.org
Mon May 19 05:57:09 PDT 2025


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/X86/X86ISelLowering.cpp
``````````

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<details>
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6f58910e5..b5356449d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -39628,7 +39628,8 @@ static bool matchBinaryPermuteShuffle(
     }
     if (ZeroHi) {
       SmallVector<int, 16> ShiftMask(NumMaskElts, SM_SentinelZero);
-      std::iota(ShiftMask.begin(), ShiftMask.begin() + NumMaskElts - ZeroHi, ZeroHi);
+      std::iota(ShiftMask.begin(), ShiftMask.begin() + NumMaskElts - ZeroHi,
+                ZeroHi);
       if (isTargetShuffleEquivalent(MaskVT, Mask, ShiftMask, DAG, V1)) {
         V2 = V1;
         V1 = getZeroVector(AlignVT, Subtarget, DAG, DL);

``````````

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https://github.com/llvm/llvm-project/pull/140538


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