[llvm] 52e1995 - [X86] Add tests showing failure to combine AVX512 shuffles to match "cross lane" SHLDQ/SRLDQ patterns using VALIGN

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-05-19T13:27:57+01:00
New Revision: 52e1995eca35da79d27576b94b614a7fd2420c41

URL: https://github.com/llvm/llvm-project/commit/52e1995eca35da79d27576b94b614a7fd2420c41
DIFF: https://github.com/llvm/llvm-project/commit/52e1995eca35da79d27576b94b614a7fd2420c41.diff

LOG: [X86] Add tests showing failure to combine AVX512 shuffles to match "cross lane" SHLDQ/SRLDQ patterns using VALIGN

We match two input shuffles, but not if one input is zero

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
index 400a3e835307f..b3b90b5f51501 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
@@ -800,6 +800,38 @@ define <8 x double> @combine_vpermi2var_8f64_as_vpermpd(<8 x double> %x0, <8 x d
   ret <8 x double> %res1
 }
 
+define <8 x i64> @combine_vpermt2var_8i64_as_valignq(<8 x i64> %x0, <8 x i64> %x1) {
+; CHECK-LABEL: combine_vpermt2var_8i64_as_valignq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    valignq {{.*#+}} zmm0 = zmm1[7],zmm0[0,1,2,3,4,5,6]
+; CHECK-NEXT:    ret{{[l|q]}}
+  %res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 15, i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6>, <8 x i64> %x0, <8 x i64> %x1, i8 -1)
+  ret <8 x i64> %res0
+}
+
+define <8 x i64> @combine_vpermt2var_8i64_as_valignq_zero(<8 x i64> %x0) {
+; CHECK-LABEL: combine_vpermt2var_8i64_as_valignq_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpmovsxbq {{.*#+}} zmm2 = [15,0,1,2,3,4,5,6]
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpermt2q %zmm0, %zmm2, %zmm1
+; CHECK-NEXT:    vmovdqa64 %zmm1, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 15, i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6>, <8 x i64> zeroinitializer, <8 x i64> %x0, i8 -1)
+  ret <8 x i64> %res0
+}
+
+define <8 x i64> @combine_vpermt2var_8i64_as_zero_valignq(<8 x i64> %x0) {
+; CHECK-LABEL: combine_vpermt2var_8i64_as_zero_valignq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; CHECK-NEXT:    vpmovsxbq {{.*#+}} zmm2 = [15,0,1,2,3,4,5,6]
+; CHECK-NEXT:    vpermt2q %zmm1, %zmm2, %zmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %res0 = call <8 x i64> @llvm.x86.avx512.maskz.vpermt2var.q.512(<8 x i64> <i64 15, i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6>, <8 x i64> %x0, <8 x i64> zeroinitializer, i8 -1)
+  ret <8 x i64> %res0
+}
+
 define <8 x i64> @combine_vpermt2var_8i64_as_vpermq(<8 x i64> %x0, <8 x i64> %x1) {
 ; CHECK-LABEL: combine_vpermt2var_8i64_as_vpermq:
 ; CHECK:       # %bb.0: