[llvm] [DAGCombine] Use isLegalExtLoad for MatchLoadCombine (PR #140536)

[David Green via llvm-commits]

https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/140536

This looks wrong to me, but I don't have a test case where it alters the generated code.

>From 9e727585b98e6d542e5200798429f57c5b7d58c8 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 9 May 2025 11:52:12 +0100
Subject: [PATCH] [DAGCombine] Use isLegalExtLoad for MatchLoadCombine

This looks wrong to me, but I don't have a test case where it alters the
generated code.
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 564cc372f595c..64fb1fcaa558f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9482,8 +9482,8 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
   // split into legal sized loads. This enables us to combine i64 load by i8
   // patterns to a couple of i32 loads on 32 bit targets.
   if (LegalOperations &&
-      !TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD,
-                            MemVT))
+      !TLI.isLoadExtLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, VT,
+                          MemVT))
     return SDValue();
 
   // Check if the bytes of the OR we are looking at match with either big or