[llvm] [AArch64] TableGen-erate SDNode descriptions (PR #140472)

[Sergei Barannikov via llvm-commits]

================
@@ -23,22 +27,20 @@ static cl::opt<bool>
                                 "to lower to librt functions"),
                        cl::init(true));
 
-bool AArch64SelectionDAGInfo::isTargetMemoryOpcode(unsigned Opcode) const {
-  return Opcode >= AArch64ISD::FIRST_MEMORY_OPCODE &&
-         Opcode <= AArch64ISD::LAST_MEMORY_OPCODE;
-}
-
-bool AArch64SelectionDAGInfo::isTargetStrictFPOpcode(unsigned Opcode) const {
-  return Opcode >= AArch64ISD::FIRST_STRICTFP_OPCODE &&
-         Opcode <= AArch64ISD::LAST_STRICTFP_OPCODE;
-}
+AArch64SelectionDAGInfo::AArch64SelectionDAGInfo()
+    : SelectionDAGGenTargetInfo(AArch64GenSDNodeInfo) {}
 
 void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
                                                const SDNode *N) const {
 #ifndef NDEBUG
   switch (N->getOpcode()) {
   default:
-    break;
+    return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
+  case AArch64ISD::SMSTART:
+  case AArch64ISD::SMSTOP:
+    // FIXME: These can't be verified by SelectionDAGGenTargetInfo as the
+    // variadic "PStateSM" operand is not a Register or RegisterMask.
----------------
s-barannikov wrote:

One way to fix this is to split these nodes into conditional/unconditional variants, another is to require three operands and pass an `undef` for the third operand when the second operand (the condition) is `Always`. This will probably require updating DAG patterns and/or `AArch64TargetLowering::AdjustInstrPostInstrSelection`. `AArch64SME.rst` may also need to be updated.


https://github.com/llvm/llvm-project/pull/140472