[llvm] [PowerPC] vector shift word/double by element size - 1 use all ones (PR #139794)

[Amy Kwan via llvm-commits]

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@@ -18456,36 +18456,78 @@ static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N,
   return SDValue();
 }
 
-SDValue PPCTargetLowering::combineVectorSHL(SDNode *N,
-                                            DAGCombinerInfo &DCI) const {
+SDValue PPCTargetLowering::combineVectorShift(SDNode *N,
+                                              DAGCombinerInfo &DCI) const {
   EVT VT = N->getValueType(0);
   assert(VT.isVector() && "Vector type expected.");
 
-  SDValue N1 = N->getOperand(1);
-  if (!Subtarget.hasP8Altivec() || N1.getOpcode() != ISD::BUILD_VECTOR ||
-      !isOperationLegal(ISD::ADD, VT))
+  unsigned Opc = N->getOpcode();
+  assert((Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
+         "Unexpected opcode.");
+
+  if (!isOperationLegal(N->getOpcode(), VT))
     return SDValue();
 
-  // For 64-bit there is no splat immediate so we want to catch shift by 1 here
-  // before the BUILD_VECTOR is replaced by a load.
   EVT EltTy = VT.getScalarType();
-  if (EltTy != MVT::i64)
+  unsigned EltBits = EltTy.getSizeInBits();
+  if (EltTy != MVT::i64 && EltTy != MVT::i32)
     return SDValue();
 
-  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(N1);
-  APInt APSplatBits, APSplatUndef;
-  unsigned SplatBitSize;
-  bool HasAnyUndefs;
-  bool BVNIsConstantSplat =
-      BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
-                           HasAnyUndefs, 0, !Subtarget.isLittleEndian());
-  if (!BVNIsConstantSplat || SplatBitSize != EltTy.getSizeInBits())
+  SDValue N1 = N->getOperand(1);
+  uint64_t SplatBits = 0;
+  bool AddSplatCase = false;
+  if (N1.getOpcode() == PPCISD::VADD_SPLAT &&
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amy-kwan wrote:

We can probably save `N1.getOpcode()` before hand, for this check and for the build vector check below.

https://github.com/llvm/llvm-project/pull/139794