[llvm] 2f05451 - RISCV: Replace most Specifier constants with relocation types
via llvm-commits
llvm-commits at lists.llvm.org
Sat May 17 10:14:37 PDT 2025
Author: Fangrui Song
Date: 2025-05-17T10:14:33-07:00
New Revision: 2f05451198e2f222ec66cec4892ada0509519290
URL: https://github.com/llvm/llvm-project/commit/2f05451198e2f222ec66cec4892ada0509519290
DIFF: https://github.com/llvm/llvm-project/commit/2f05451198e2f222ec66cec4892ada0509519290.diff
LOG: RISCV: Replace most Specifier constants with relocation types
... as they map directly and we don't utilize -Wswitch.
Retained VK_*_LO constants for lowering to LO_I or LO_S.
The Sparc port has eliminated all Specifier constants (commit
003fa7731d81a47c98e9c55f80d509933c9b91f6), and the LoongArch port is
nearly free of them (#138632).
Pull Request: https://github.com/llvm/llvm-project/pull/138644
Added:
Modified:
bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
Removed:
################################################################################
diff --git a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
index 391c1866c810a..ae9b22e4051dc 100644
--- a/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
+++ b/bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
@@ -247,7 +247,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
Inst.clear();
Inst.addOperand(MCOperand::createExpr(RISCVMCExpr::create(
MCSymbolRefExpr::create(Target, MCSymbolRefExpr::VK_None, *Ctx),
- RISCVMCExpr::VK_CALL, *Ctx)));
+ ELF::R_RISCV_CALL_PLT, *Ctx)));
}
void createCall(MCInst &Inst, const MCSymbol *Target,
@@ -435,19 +435,19 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
case ELF::R_RISCV_TLS_GD_HI20:
// The GOT is reused so no need to create GOT relocations
case ELF::R_RISCV_PCREL_HI20:
- return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_HI, Ctx);
+ return RISCVMCExpr::create(Expr, ELF::R_RISCV_PCREL_HI20, Ctx);
case ELF::R_RISCV_PCREL_LO12_I:
case ELF::R_RISCV_PCREL_LO12_S:
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_PCREL_LO, Ctx);
case ELF::R_RISCV_HI20:
- return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_HI, Ctx);
+ return RISCVMCExpr::create(Expr, ELF::R_RISCV_HI20, Ctx);
case ELF::R_RISCV_LO12_I:
case ELF::R_RISCV_LO12_S:
return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_LO, Ctx);
case ELF::R_RISCV_CALL:
- return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL, Ctx);
+ return RISCVMCExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
case ELF::R_RISCV_CALL_PLT:
- return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_CALL_PLT, Ctx);
+ return RISCVMCExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
}
}
@@ -472,8 +472,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
switch (cast<RISCVMCExpr>(ImmExpr)->getSpecifier()) {
default:
return false;
- case RISCVMCExpr::VK_CALL:
- case RISCVMCExpr::VK_CALL_PLT:
+ case ELF::R_RISCV_CALL_PLT:
return true;
}
}
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index a1c9091c95b48..f64307babab07 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -583,7 +583,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- (VK == RISCVMCExpr::VK_CALL || VK == RISCVMCExpr::VK_CALL_PLT);
+ VK == ELF::R_RISCV_CALL_PLT;
}
bool isPseudoJumpSymbol() const {
@@ -594,7 +594,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- VK == RISCVMCExpr::VK_CALL;
+ VK == ELF::R_RISCV_CALL_PLT;
}
bool isTPRelAddSymbol() const {
@@ -605,7 +605,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- VK == RISCVMCExpr::VK_TPREL_ADD;
+ VK == ELF::R_RISCV_TPREL_ADD;
}
bool isTLSDESCCallSymbol() const {
@@ -616,7 +616,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- VK == RISCVMCExpr::VK_TLSDESC_CALL;
+ VK == ELF::R_RISCV_TLSDESC_CALL;
}
bool isCSRSystemRegister() const { return isSystemRegister(); }
@@ -868,8 +868,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
(VK == RISCVMCExpr::VK_LO || VK == RISCVMCExpr::VK_PCREL_LO ||
VK == RISCVMCExpr::VK_TPREL_LO ||
- VK == RISCVMCExpr::VK_TLSDESC_LOAD_LO ||
- VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
+ VK == ELF::R_RISCV_TLSDESC_LOAD_LO12 ||
+ VK == ELF::R_RISCV_TLSDESC_ADD_LO12);
}
bool isSImm12Lsb00000() const {
@@ -912,7 +912,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- (VK == RISCVMCExpr::VK_HI || VK == RISCVMCExpr::VK_TPREL_HI);
+ (VK == ELF::R_RISCV_HI20 || VK == ELF::R_RISCV_TPREL_HI20);
}
bool isUImm20AUIPC() const {
@@ -925,10 +925,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCExpr::Specifier VK = RISCVMCExpr::VK_None;
return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
- (VK == RISCVMCExpr::VK_PCREL_HI || VK == RISCVMCExpr::VK_GOT_HI ||
- VK == RISCVMCExpr::VK_TLS_GOT_HI ||
- VK == RISCVMCExpr::VK_TLS_GD_HI ||
- VK == RISCVMCExpr::VK_TLSDESC_HI);
+ (VK == ELF::R_RISCV_PCREL_HI20 || VK == ELF::R_RISCV_GOT_HI20 ||
+ VK == ELF::R_RISCV_TLS_GOT_HI20 || VK == ELF::R_RISCV_TLS_GD_HI20 ||
+ VK == ELF::R_RISCV_TLSDESC_HI20);
}
bool isImmZero() const {
@@ -2180,7 +2179,7 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
}
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
- RISCVMCExpr::Specifier Kind = RISCVMCExpr::VK_CALL_PLT;
+ RISCVMCExpr::Specifier Kind = ELF::R_RISCV_CALL_PLT;
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
Res = MCSymbolRefExpr::create(Sym, getContext());
@@ -2200,7 +2199,7 @@ ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
if (Res->getKind() != MCExpr::ExprKind::SymbolRef)
return Error(S, "operand must be a valid jump target");
- Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_CALL, getContext());
+ Res = RISCVMCExpr::create(Res, ELF::R_RISCV_CALL_PLT, getContext());
Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
return ParseStatus::Success;
}
@@ -3421,7 +3420,7 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
- emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_PCREL_HI,
+ emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_PCREL_HI20,
RISCV::ADDI, IDLoc, Out);
}
@@ -3436,7 +3435,7 @@ void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
- emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_GOT_HI,
+ emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_GOT_HI20,
SecondOpcode, IDLoc, Out);
}
@@ -3466,7 +3465,7 @@ void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
- emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GOT_HI,
+ emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GOT_HI20,
SecondOpcode, IDLoc, Out);
}
@@ -3480,7 +3479,7 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
MCRegister DestReg = Inst.getOperand(0).getReg();
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
- emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GD_HI,
+ emitAuipcInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GD_HI20,
RISCV::ADDI, IDLoc, Out);
}
@@ -3506,7 +3505,7 @@ void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
}
const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
- emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_PCREL_HI, Opcode,
+ emitAuipcInstPair(DestReg, TmpReg, Symbol, ELF::R_RISCV_PCREL_HI20, Opcode,
IDLoc, Out);
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index 35e75489794f7..42095d4a2b149 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -54,15 +54,15 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
unsigned Kind = Fixup.getTargetKind();
auto Spec = RISCVMCExpr::Specifier(Target.getSpecifier());
switch (Spec) {
- case RISCVMCExpr::VK_TPREL_HI:
- case RISCVMCExpr::VK_TLS_GOT_HI:
- case RISCVMCExpr::VK_TLS_GD_HI:
- case RISCVMCExpr::VK_TLSDESC_HI:
+ case ELF::R_RISCV_TPREL_HI20:
+ case ELF::R_RISCV_TLS_GOT_HI20:
+ case ELF::R_RISCV_TLS_GD_HI20:
+ case ELF::R_RISCV_TLSDESC_HI20:
if (auto *SA = Target.getAddSym())
cast<MCSymbolELF>(SA)->setType(ELF::STT_TLS);
break;
- case RISCVMCExpr::VK_PLTPCREL:
- case RISCVMCExpr::VK_GOTPCREL:
+ case ELF::R_RISCV_PLT32:
+ case ELF::R_RISCV_GOT32_PCREL:
if (Kind == FK_Data_4)
break;
Ctx.reportError(Fixup.getLoc(),
@@ -124,15 +124,12 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
return ELF::R_RISCV_NONE;
case FK_Data_4:
if (Expr->getKind() == MCExpr::Target) {
- switch (cast<RISCVMCExpr>(Expr)->getSpecifier()) {
- case RISCVMCExpr::VK_32_PCREL:
- return ELF::R_RISCV_32_PCREL;
- case RISCVMCExpr::VK_GOTPCREL:
- return ELF::R_RISCV_GOT32_PCREL;
- case RISCVMCExpr::VK_PLTPCREL:
- return ELF::R_RISCV_PLT32;
- default:
- break;
+ auto Spec = cast<RISCVMCExpr>(Expr)->getSpecifier();
+ switch (Spec) {
+ case ELF::R_RISCV_32_PCREL:
+ case ELF::R_RISCV_GOT32_PCREL:
+ case ELF::R_RISCV_PLT32:
+ return Spec;
}
}
return ELF::R_RISCV_32;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
index d1e8ec9d6b54a..e75bc521d47ca 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
@@ -13,6 +13,7 @@
#include "RISCVMCAsmInfo.h"
#include "MCTargetDesc/RISCVMCExpr.h"
#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/TargetParser/Triple.h"
@@ -44,5 +45,5 @@ const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym,
MCContext &Ctx = Streamer.getContext();
const MCExpr *ME = MCSymbolRefExpr::create(Sym, Ctx);
assert(Encoding & dwarf::DW_EH_PE_sdata4 && "Unexpected encoding");
- return RISCVMCExpr::create(ME, RISCVMCExpr::VK_32_PCREL, Ctx);
+ return RISCVMCExpr::create(ME, ELF::R_RISCV_32_PCREL, Ctx);
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 7486618782e6c..23f7a6025daf1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -206,7 +206,7 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
"Expected expression as third input to TP-relative add");
const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
- assert(Expr && Expr->getSpecifier() == RISCVMCExpr::VK_TPREL_ADD &&
+ assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
"Expected tprel_add relocation on TP-relative symbol");
// Emit the correct tprel_add relocation for the symbol.
@@ -573,20 +573,19 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
bool RelaxCandidate = false;
if (Kind == MCExpr::Target) {
const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
-
+ FixupKind = RVExpr->getSpecifier();
switch (RVExpr->getSpecifier()) {
- case RISCVMCExpr::VK_None:
- case RISCVMCExpr::VK_32_PCREL:
- case RISCVMCExpr::VK_GOTPCREL:
- case RISCVMCExpr::VK_PLTPCREL:
- llvm_unreachable("unhandled specifier");
- case RISCVMCExpr::VK_TPREL_ADD:
+ default:
+ assert(FixupKind && FixupKind < FirstTargetFixupKind &&
+ "invalid specifier");
+ break;
+ case ELF::R_RISCV_TPREL_ADD:
// tprel_add is only used to indicate that a relocation should be emitted
// for an add instruction used in TP-relative addressing. It should not be
// expanded as if representing an actual instruction operand and so to
// encounter it here is an error.
llvm_unreachable(
- "VK_TPREL_ADD should not represent an instruction operand");
+ "ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
case RISCVMCExpr::VK_LO:
if (MIFrm == RISCVII::InstFormatI)
FixupKind = RISCV::fixup_riscv_lo12_i;
@@ -596,7 +595,7 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
llvm_unreachable("VK_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_HI:
+ case ELF::R_RISCV_HI20:
FixupKind = RISCV::fixup_riscv_hi20;
RelaxCandidate = true;
break;
@@ -609,13 +608,10 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_PCREL_HI:
+ case ELF::R_RISCV_PCREL_HI20:
FixupKind = RISCV::fixup_riscv_pcrel_hi20;
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_GOT_HI:
- FixupKind = ELF::R_RISCV_GOT_HI20;
- break;
case RISCVMCExpr::VK_TPREL_LO:
if (MIFrm == RISCVII::InstFormatI)
FixupKind = ELF::R_RISCV_TPREL_LO12_I;
@@ -625,36 +621,13 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_TPREL_HI:
- FixupKind = ELF::R_RISCV_TPREL_HI20;
+ case ELF::R_RISCV_TPREL_HI20:
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_TLS_GOT_HI:
- FixupKind = ELF::R_RISCV_TLS_GOT_HI20;
- break;
- case RISCVMCExpr::VK_TLS_GD_HI:
- FixupKind = ELF::R_RISCV_TLS_GD_HI20;
- break;
- case RISCVMCExpr::VK_CALL:
- FixupKind = RISCV::fixup_riscv_call;
- RelaxCandidate = true;
- break;
- case RISCVMCExpr::VK_CALL_PLT:
+ case ELF::R_RISCV_CALL_PLT:
FixupKind = RISCV::fixup_riscv_call_plt;
RelaxCandidate = true;
break;
- case RISCVMCExpr::VK_TLSDESC_HI:
- FixupKind = ELF::R_RISCV_TLSDESC_HI20;
- break;
- case RISCVMCExpr::VK_TLSDESC_LOAD_LO:
- FixupKind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
- break;
- case RISCVMCExpr::VK_TLSDESC_ADD_LO:
- FixupKind = ELF::R_RISCV_TLSDESC_ADD_LO12;
- break;
- case RISCVMCExpr::VK_TLSDESC_CALL:
- FixupKind = ELF::R_RISCV_TLSDESC_CALL;
- break;
case RISCVMCExpr::VK_QC_ABS20:
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
break;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
index 31a3ace2c0477..8f0aa7aeff208 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -34,7 +34,7 @@ const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, Specifier S,
void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
Specifier S = getSpecifier();
- bool HasVariant = ((S != VK_None) && (S != VK_CALL) && (S != VK_CALL_PLT));
+ bool HasVariant = S != VK_None && S != ELF::R_RISCV_CALL_PLT;
if (HasVariant)
OS << '%' << getSpecifierName(S) << '(';
@@ -106,23 +106,23 @@ std::optional<RISCVMCExpr::Specifier>
RISCVMCExpr::getSpecifierForName(StringRef name) {
return StringSwitch<std::optional<RISCVMCExpr::Specifier>>(name)
.Case("lo", VK_LO)
- .Case("hi", VK_HI)
+ .Case("hi", ELF::R_RISCV_HI20)
.Case("pcrel_lo", VK_PCREL_LO)
- .Case("pcrel_hi", VK_PCREL_HI)
- .Case("got_pcrel_hi", VK_GOT_HI)
+ .Case("pcrel_hi", ELF::R_RISCV_PCREL_HI20)
+ .Case("got_pcrel_hi", ELF::R_RISCV_GOT_HI20)
.Case("tprel_lo", VK_TPREL_LO)
- .Case("tprel_hi", VK_TPREL_HI)
- .Case("tprel_add", VK_TPREL_ADD)
- .Case("tls_ie_pcrel_hi", VK_TLS_GOT_HI)
- .Case("tls_gd_pcrel_hi", VK_TLS_GD_HI)
- .Case("tlsdesc_hi", VK_TLSDESC_HI)
- .Case("tlsdesc_load_lo", VK_TLSDESC_LOAD_LO)
- .Case("tlsdesc_add_lo", VK_TLSDESC_ADD_LO)
- .Case("tlsdesc_call", VK_TLSDESC_CALL)
+ .Case("tprel_hi", ELF::R_RISCV_TPREL_HI20)
+ .Case("tprel_add", ELF::R_RISCV_TPREL_ADD)
+ .Case("tls_ie_pcrel_hi", ELF::R_RISCV_TLS_GOT_HI20)
+ .Case("tls_gd_pcrel_hi", ELF::R_RISCV_TLS_GD_HI20)
+ .Case("tlsdesc_hi", ELF::R_RISCV_TLSDESC_HI20)
+ .Case("tlsdesc_load_lo", ELF::R_RISCV_TLSDESC_LOAD_LO12)
+ .Case("tlsdesc_add_lo", ELF::R_RISCV_TLSDESC_ADD_LO12)
+ .Case("tlsdesc_call", ELF::R_RISCV_TLSDESC_CALL)
.Case("qc.abs20", VK_QC_ABS20)
// Used in data directives
- .Case("pltpcrel", VK_PLTPCREL)
- .Case("gotpcrel", VK_GOTPCREL)
+ .Case("pltpcrel", ELF::R_RISCV_PLT32)
+ .Case("gotpcrel", ELF::R_RISCV_GOT32_PCREL)
.Default(std::nullopt);
}
@@ -132,41 +132,39 @@ StringRef RISCVMCExpr::getSpecifierName(Specifier S) {
llvm_unreachable("not used as %specifier()");
case VK_LO:
return "lo";
- case VK_HI:
+ case ELF::R_RISCV_HI20:
return "hi";
case VK_PCREL_LO:
return "pcrel_lo";
- case VK_PCREL_HI:
+ case ELF::R_RISCV_PCREL_HI20:
return "pcrel_hi";
- case VK_GOT_HI:
+ case ELF::R_RISCV_GOT_HI20:
return "got_pcrel_hi";
case VK_TPREL_LO:
return "tprel_lo";
- case VK_TPREL_HI:
+ case ELF::R_RISCV_TPREL_HI20:
return "tprel_hi";
- case VK_TPREL_ADD:
+ case ELF::R_RISCV_TPREL_ADD:
return "tprel_add";
- case VK_TLS_GOT_HI:
+ case ELF::R_RISCV_TLS_GOT_HI20:
return "tls_ie_pcrel_hi";
- case VK_TLSDESC_HI:
+ case ELF::R_RISCV_TLSDESC_HI20:
return "tlsdesc_hi";
- case VK_TLSDESC_LOAD_LO:
+ case ELF::R_RISCV_TLSDESC_LOAD_LO12:
return "tlsdesc_load_lo";
- case VK_TLSDESC_ADD_LO:
+ case ELF::R_RISCV_TLSDESC_ADD_LO12:
return "tlsdesc_add_lo";
- case VK_TLSDESC_CALL:
+ case ELF::R_RISCV_TLSDESC_CALL:
return "tlsdesc_call";
- case VK_TLS_GD_HI:
+ case ELF::R_RISCV_TLS_GD_HI20:
return "tls_gd_pcrel_hi";
- case VK_CALL:
- return "call";
- case VK_CALL_PLT:
+ case ELF::R_RISCV_CALL_PLT:
return "call_plt";
- case VK_32_PCREL:
+ case ELF::R_RISCV_32_PCREL:
return "32_pcrel";
- case VK_GOTPCREL:
+ case ELF::R_RISCV_GOT32_PCREL:
return "gotpcrel";
- case VK_PLTPCREL:
+ case ELF::R_RISCV_PLT32:
return "pltpcrel";
case VK_QC_ABS20:
return "qc.abs20";
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
index e0aa7ff244521..917c59ab3961b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
@@ -15,6 +15,7 @@
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVMCEXPR_H
#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixup.h"
namespace llvm {
@@ -22,27 +23,17 @@ class StringRef;
class RISCVMCExpr : public MCTargetExpr {
public:
- enum Specifier : uint8_t {
+ using Specifier = uint16_t;
+ // Specifiers mapping to relocation types below FirstTargetFixupKind are
+ // encoded literally, with these exceptions:
+ enum {
VK_None,
- VK_LO = MCSymbolRefExpr::FirstTargetSpecifier,
- VK_HI,
+ // Specifiers mapping to distinct relocation types.
+ VK_LO = FirstTargetFixupKind,
VK_PCREL_LO,
- VK_PCREL_HI,
- VK_GOT_HI,
VK_TPREL_LO,
- VK_TPREL_HI,
- VK_TPREL_ADD,
- VK_TLS_GOT_HI,
- VK_TLS_GD_HI,
- VK_CALL,
- VK_CALL_PLT,
- VK_32_PCREL,
- VK_GOTPCREL,
- VK_PLTPCREL,
- VK_TLSDESC_HI,
- VK_TLSDESC_LOAD_LO,
- VK_TLSDESC_ADD_LO,
- VK_TLSDESC_CALL,
+ // Vendor-specific relocation types might conflict across vendors.
+ // Refer to them using Specifier constants.
VK_QC_ABS20,
};
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 5aa323abf068f..72f1596d79a02 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -630,7 +630,7 @@ void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
Sym = OutContext.getOrCreateSymbol(SymName);
}
auto Res = MCSymbolRefExpr::create(Sym, OutContext);
- auto Expr = RISCVMCExpr::create(Res, RISCVMCExpr::VK_CALL, OutContext);
+ auto Expr = RISCVMCExpr::create(Res, ELF::R_RISCV_CALL_PLT, OutContext);
EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
}
@@ -741,7 +741,7 @@ void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
- auto Expr = RISCVMCExpr::create(HwasanTagMismatchV2Ref, RISCVMCExpr::VK_CALL,
+ auto Expr = RISCVMCExpr::create(HwasanTagMismatchV2Ref, ELF::R_RISCV_CALL_PLT,
OutContext);
for (auto &P : HwasanMemaccessSymbols) {
@@ -966,49 +966,49 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
Kind = RISCVMCExpr::VK_None;
break;
case RISCVII::MO_CALL:
- Kind = RISCVMCExpr::VK_CALL_PLT;
+ Kind = ELF::R_RISCV_CALL_PLT;
break;
case RISCVII::MO_LO:
Kind = RISCVMCExpr::VK_LO;
break;
case RISCVII::MO_HI:
- Kind = RISCVMCExpr::VK_HI;
+ Kind = ELF::R_RISCV_HI20;
break;
case RISCVII::MO_PCREL_LO:
Kind = RISCVMCExpr::VK_PCREL_LO;
break;
case RISCVII::MO_PCREL_HI:
- Kind = RISCVMCExpr::VK_PCREL_HI;
+ Kind = ELF::R_RISCV_PCREL_HI20;
break;
case RISCVII::MO_GOT_HI:
- Kind = RISCVMCExpr::VK_GOT_HI;
+ Kind = ELF::R_RISCV_GOT_HI20;
break;
case RISCVII::MO_TPREL_LO:
Kind = RISCVMCExpr::VK_TPREL_LO;
break;
case RISCVII::MO_TPREL_HI:
- Kind = RISCVMCExpr::VK_TPREL_HI;
+ Kind = ELF::R_RISCV_TPREL_HI20;
break;
case RISCVII::MO_TPREL_ADD:
- Kind = RISCVMCExpr::VK_TPREL_ADD;
+ Kind = ELF::R_RISCV_TPREL_ADD;
break;
case RISCVII::MO_TLS_GOT_HI:
- Kind = RISCVMCExpr::VK_TLS_GOT_HI;
+ Kind = ELF::R_RISCV_TLS_GOT_HI20;
break;
case RISCVII::MO_TLS_GD_HI:
- Kind = RISCVMCExpr::VK_TLS_GD_HI;
+ Kind = ELF::R_RISCV_TLS_GD_HI20;
break;
case RISCVII::MO_TLSDESC_HI:
- Kind = RISCVMCExpr::VK_TLSDESC_HI;
+ Kind = ELF::R_RISCV_TLSDESC_HI20;
break;
case RISCVII::MO_TLSDESC_LOAD_LO:
- Kind = RISCVMCExpr::VK_TLSDESC_LOAD_LO;
+ Kind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
break;
case RISCVII::MO_TLSDESC_ADD_LO:
- Kind = RISCVMCExpr::VK_TLSDESC_ADD_LO;
+ Kind = ELF::R_RISCV_TLSDESC_ADD_LO12;
break;
case RISCVII::MO_TLSDESC_CALL:
- Kind = RISCVMCExpr::VK_TLSDESC_CALL;
+ Kind = ELF::R_RISCV_TLSDESC_CALL;
break;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
index 57c0af7ce5dca..3cb5c7e13dd78 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
@@ -27,7 +27,7 @@ void RISCVELFTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
- PLTPCRelativeSpecifier = RISCVMCExpr::VK_PLTPCREL;
+ PLTPCRelativeSpecifier = ELF::R_RISCV_PLT32;
SupportIndirectSymViaGOTPCRel = true;
SmallDataSection = getContext().getELFSection(
@@ -53,7 +53,7 @@ const MCExpr *RISCVELFTargetObjectFile::getIndirectSymViaGOTPCRel(
const MCExpr *Res = MCSymbolRefExpr::create(Sym, Ctx);
Res = MCBinaryExpr::createAdd(
Res, MCConstantExpr::create(Offset + MV.getConstant(), Ctx), Ctx);
- return RISCVMCExpr::create(Res, RISCVMCExpr::VK_GOTPCREL, Ctx);
+ return RISCVMCExpr::create(Res, ELF::R_RISCV_GOT32_PCREL, Ctx);
}
// A address must be loaded from a small section if its size is less than the
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