[llvm] 9e22f96 - [DAGCombiner] Fix a "subtraction if above a constant threshold" miscompile (#140042)
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Sat May 17 03:18:55 PDT 2025
Author: Piotr Fusik
Date: 2025-05-17T12:18:52+02:00
New Revision: 9e22f9611a5b61f412dbf1b72a4fe2d2089eeec2
URL: https://github.com/llvm/llvm-project/commit/9e22f9611a5b61f412dbf1b72a4fe2d2089eeec2
DIFF: https://github.com/llvm/llvm-project/commit/9e22f9611a5b61f412dbf1b72a4fe2d2089eeec2.diff
LOG: [DAGCombiner] Fix a "subtraction if above a constant threshold" miscompile (#140042)
This fixes #135194 incorrectly reusing the existing `add nuw/nsw`
while the transformed code relies on an unsigned wrap.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/RISCV/rv32zbb.ll
llvm/test/CodeGen/RISCV/rv64zbb.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4be3363e56987..68693cef06ee6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12156,11 +12156,21 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
// (select (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
APInt C;
if (sd_match(Cond1, m_ConstInt(C)) && hasUMin(VT)) {
- if ((CC == ISD::SETUGT && Cond0 == N2 &&
- sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C)))) ||
- (CC == ISD::SETULT && Cond0 == N1 &&
- sd_match(N2, m_Add(m_Specific(N1), m_SpecificInt(-C)))))
- return DAG.getNode(ISD::UMIN, DL, VT, N1, N2);
+ if (CC == ISD::SETUGT && Cond0 == N2 &&
+ sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C)))) {
+ // The resulting code relies on an unsigned wrap in ADD.
+ // Recreating ADD to drop possible nuw/nsw flags.
+ SDValue AddC = DAG.getConstant(~C, DL, VT);
+ SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N2, AddC);
+ return DAG.getNode(ISD::UMIN, DL, VT, Add, N2);
+ }
+ if (CC == ISD::SETULT && Cond0 == N1 &&
+ sd_match(N2, m_Add(m_Specific(N1), m_SpecificInt(-C)))) {
+ // Ditto.
+ SDValue AddC = DAG.getConstant(-C, DL, VT);
+ SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, AddC);
+ return DAG.getNode(ISD::UMIN, DL, VT, N1, Add);
+ }
}
}
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
index 0f2284637ca6a..62bc7b3336a5c 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -1917,3 +1917,55 @@ define i32 @sub_if_uge_C_swapped_i32(i32 %x) {
%cond = select i1 %cmp, i32 %x, i32 %sub
ret i32 %cond
}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; RV32I-LABEL: sub_if_uge_C_nsw_i7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ori a0, a0, 51
+; RV32I-NEXT: andi a1, a0, 127
+; RV32I-NEXT: sltiu a1, a1, 111
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: andi a1, a1, 17
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: sub_if_uge_C_nsw_i7:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: ori a0, a0, 51
+; RV32ZBB-NEXT: andi a1, a0, 127
+; RV32ZBB-NEXT: addi a0, a0, 17
+; RV32ZBB-NEXT: andi a0, a0, 92
+; RV32ZBB-NEXT: minu a0, a0, a1
+; RV32ZBB-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; RV32I-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV32I: # %bb.0:
+; RV32I-NEXT: ori a0, a0, 51
+; RV32I-NEXT: andi a1, a0, 127
+; RV32I-NEXT: sltiu a1, a1, 111
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: andi a1, a1, 17
+; RV32I-NEXT: add a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: ori a0, a0, 51
+; RV32ZBB-NEXT: andi a1, a0, 127
+; RV32ZBB-NEXT: addi a0, a0, 17
+; RV32ZBB-NEXT: andi a0, a0, 92
+; RV32ZBB-NEXT: minu a0, a1, a0
+; RV32ZBB-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index 3cd1931b6ae4c..97b8b2aa5e525 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -2118,3 +2118,55 @@ define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
%cond = select i1 %cmp, i32 %x, i32 %sub
ret i32 %cond
}
+
+define i7 @sub_if_uge_C_nsw_i7(i7 %a) {
+; RV64I-LABEL: sub_if_uge_C_nsw_i7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 51
+; RV64I-NEXT: andi a1, a0, 127
+; RV64I-NEXT: sltiu a1, a1, 111
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, 17
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_nsw_i7:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: ori a0, a0, 51
+; RV64ZBB-NEXT: andi a1, a0, 127
+; RV64ZBB-NEXT: addi a0, a0, 17
+; RV64ZBB-NEXT: andi a0, a0, 92
+; RV64ZBB-NEXT: minu a0, a0, a1
+; RV64ZBB-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ugt i7 %x, -18
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %add, i7 %x
+ ret i7 %s
+}
+
+define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) {
+; RV64I-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV64I: # %bb.0:
+; RV64I-NEXT: ori a0, a0, 51
+; RV64I-NEXT: andi a1, a0, 127
+; RV64I-NEXT: sltiu a1, a1, 111
+; RV64I-NEXT: addi a1, a1, -1
+; RV64I-NEXT: andi a1, a1, 17
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_C_swapped_nsw_i7:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: ori a0, a0, 51
+; RV64ZBB-NEXT: andi a1, a0, 127
+; RV64ZBB-NEXT: addi a0, a0, 17
+; RV64ZBB-NEXT: andi a0, a0, 92
+; RV64ZBB-NEXT: minu a0, a1, a0
+; RV64ZBB-NEXT: ret
+ %x = or i7 %a, 51
+ %c = icmp ult i7 %x, -17
+ %add = add nsw i7 %x, 17
+ %s = select i1 %c, i7 %x, i7 %add
+ ret i7 %s
+}
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