[llvm] [RISCV] Add scheduling model for SiFive P800 processors (PR #139316)
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Fri May 16 13:23:00 PDT 2025
https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/139316
>From d6eca08f431cd2d5b788be1c815b9709fcca738b Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Mon, 28 Apr 2025 14:59:56 -0700
Subject: [PATCH 1/3] [RISCV] Add scheduling model for SiFive P800 processors
---
llvm/lib/Target/RISCV/RISCV.td | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td | 1184 ++++
.../tools/llvm-mca/RISCV/SiFiveP800/div.s | 854 +++
.../tools/llvm-mca/RISCV/SiFiveP800/fmadd.s | 199 +
.../tools/llvm-mca/RISCV/SiFiveP800/load.s | 86 +
.../tools/llvm-mca/RISCV/SiFiveP800/mask.s | 151 +
.../llvm-mca/RISCV/SiFiveP800/mul-cpop.s | 85 +
.../llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s | 567 ++
.../llvm-mca/RISCV/SiFiveP800/vlse-vsse.s | 341 ++
.../llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s | 4752 +++++++++++++++++
.../llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s | 613 +++
.../tools/llvm-mca/RISCV/SiFiveP800/vmv.s | 694 +++
.../tools/llvm-mca/RISCV/SiFiveP800/zfa.s | 98 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvbb.s | 483 ++
.../tools/llvm-mca/RISCV/SiFiveP800/zvbc.s | 135 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvkg.s | 150 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvkned.s | 226 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s | 180 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvksed.s | 136 +
.../tools/llvm-mca/RISCV/SiFiveP800/zvksh.s | 121 +
21 files changed, 11057 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/div.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/fmadd.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/load.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mask.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-cpop.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vmv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbb.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbc.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkned.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksed.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksh.s
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 7f96c6718ffa9..e322ae340349c 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -58,6 +58,7 @@ include "RISCVSchedSiFive7.td"
include "RISCVSchedSiFiveP400.td"
include "RISCVSchedSiFiveP500.td"
include "RISCVSchedSiFiveP600.td"
+include "RISCVSchedSiFiveP800.td"
include "RISCVSchedSpacemitX60.td"
include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedSyntacoreSCR345.td"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index db57f5c4da24e..735997de94e81 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -365,7 +365,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
-def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", SiFiveP800Model,
!listconcat(RVA23U64Features,
[FeatureStdExtZama16b,
FeatureStdExtZfh,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
new file mode 100644
index 0000000000000..f226f1f683f5e
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -0,0 +1,1184 @@
+//==- RISCVSchedSiFiveP800.td - SiFiveP800 Scheduling Defs ---*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFiveP800, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFiveP800IsWorstCaseMX<string mx, list<string> MxList> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+class SiFiveP800IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ int SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+// 1 Micro-Op per cycle.
+class SiFiveP800GetLMulCycles<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+// Latency for segmented loads and stores are calculated as vl.
+class SiFiveP800GetCyclesSegmented<string mx, int sew> {
+ defvar VLEN = 128;
+ int c = !cond(
+ !eq(mx, "M1") : !div(VLEN, sew),
+ !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
+ !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
+ !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
+ !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
+ );
+}
+
+class SiFiveP800VSM3CCycles<string mx> {
+ // c = ceil(LMUL / 2)
+ int c = !cond(!eq(mx, "M2") : 1,
+ !eq(mx, "M4") : 2,
+ !eq(mx, "M8") : 4,
+ true : 1);
+}
+
+// SiFiveP800 machine model for scheduling and other instruction cost heuristics.
+def SiFiveP800Model : SchedMachineModel {
+ let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
+ let MicroOpBufferSize = 288; // Max micro-ops that can be buffered.
+ let LoadLatency = 4; // Cycles for loads to access the cache.
+ let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
+ let PostRAScheduler = true;
+ let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
+ HasVendorXSfvqmaccqoq, HasVendorXSfvqmaccdod];
+ let CompleteModel = false;
+}
+
+let SchedModel = SiFiveP800Model in {
+
+def SiFiveP800IEXQ0 : ProcResource<1>;
+def SiFiveP800IEXQ1 : ProcResource<1>;
+def SiFiveP800IEXQ2 : ProcResource<1>;
+def SiFiveP800IEXQ3 : ProcResource<1>;
+def SiFiveP800IEXQ4 : ProcResource<1>;
+def SiFiveP800IEXQ5 : ProcResource<1>;
+def SiFiveP800FEXQ0 : ProcResource<1>;
+def SiFiveP800FEXQ1 : ProcResource<1>;
+
+// Two Load/Store ports that can issue either two loads, two stores, or one load
+// and one store.
+def SiFiveP800LDST : ProcResource<2>;
+// One additional port that can only handle loads.
+def SiFiveP800LD : ProcResource<1>;
+def SiFiveP800Load : ProcResGroup<[SiFiveP800LDST, SiFiveP800LD]>;
+
+// 6-wide pipeline with 6 ALU pipes.
+def SiFiveP800IntArith : ProcResGroup<[SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3]>;
+defvar SiFiveP800SYS = SiFiveP800IEXQ1;
+defvar SiFiveP800CMOV = SiFiveP800IEXQ3;
+defvar SiFiveP800I2F = SiFiveP800IEXQ3;
+def SiFiveP800Mul : ProcResGroup<[SiFiveP800IEXQ1, SiFiveP800IEXQ3]>;
+def SiFiveP800Branch : ProcResGroup<[SiFiveP800IEXQ4, SiFiveP800IEXQ5]>;
+def SiFiveP800Div : ProcResource<1>;
+
+def SiFiveP800FloatArith : ProcResGroup<[SiFiveP800FEXQ0, SiFiveP800FEXQ1]>;
+defvar SiFiveP800F2I = SiFiveP800FEXQ0;
+def SiFiveP800FloatDiv : ProcResource<1>;
+
+// Vector pipeline
+// VEXQ0 handle Mask, Simple Slide instructions,
+// VEXQ1 handle Complex Slide, Permutation, Reductions, Divide instructions.
+// Other vector instructions can be done in VEXQ0 and VEXQ1.
+def SiFiveP800VEXQ0 : ProcResource<1>;
+def SiFiveP800VEXQ1 : ProcResource<1>;
+def SiFiveP800VectorArith : ProcResGroup<[SiFiveP800VEXQ0, SiFiveP800VEXQ1]>;
+
+def SiFiveP800VLD : ProcResource<1>;
+def SiFiveP800VST : ProcResource<1>;
+def SiFiveP800VDiv : ProcResource<1>;
+def SiFiveP800VFloatDiv : ProcResource<1>;
+
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU, [SiFiveP800IntArith]>;
+def : WriteRes<WriteIALU32, [SiFiveP800IntArith]>;
+def : WriteRes<WriteShiftImm, [SiFiveP800IntArith]>;
+def : WriteRes<WriteShiftImm32, [SiFiveP800IntArith]>;
+def : WriteRes<WriteShiftReg, [SiFiveP800IntArith]>;
+def : WriteRes<WriteShiftReg32, [SiFiveP800IntArith]>;
+// Branching
+def : WriteRes<WriteJmp, [SiFiveP800Branch]>;
+def : WriteRes<WriteJal, [SiFiveP800Branch]>;
+def : WriteRes<WriteJalr, [SiFiveP800Branch]>;
+
+// CMOV
+def P800WriteCMOV : SchedWriteRes<[SiFiveP800Branch, SiFiveP800CMOV]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
+}
+def : InstRW<[P800WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;
+
+let Latency = 2 in {
+// Integer multiplication
+def : WriteRes<WriteIMul, [SiFiveP800Mul]>;
+def : WriteRes<WriteIMul32, [SiFiveP800Mul]>;
+// cpop[w] look exactly like multiply.
+def : WriteRes<WriteCPOP, [SiFiveP800Mul]>;
+def : WriteRes<WriteCPOP32, [SiFiveP800Mul]>;
+}
+
+// Integer division
+def : WriteRes<WriteIDiv, [SiFiveP800IEXQ2, SiFiveP800Div]> {
+ let Latency = 35;
+ let ReleaseAtCycles = [1, 34];
+}
+def : WriteRes<WriteIDiv32, [SiFiveP800IEXQ2, SiFiveP800Div]> {
+ let Latency = 20;
+ let ReleaseAtCycles = [1, 19];
+}
+
+// Integer remainder
+def : WriteRes<WriteIRem, [SiFiveP800IEXQ2, SiFiveP800Div]> {
+ let Latency = 35;
+ let ReleaseAtCycles = [1, 34];
+}
+def : WriteRes<WriteIRem32, [SiFiveP800IEXQ2, SiFiveP800Div]> {
+ let Latency = 20;
+ let ReleaseAtCycles = [1, 19];
+}
+
+// Bitmanip
+def : WriteRes<WriteRotateImm, [SiFiveP800IntArith]>;
+def : WriteRes<WriteRotateImm32, [SiFiveP800IntArith]>;
+def : WriteRes<WriteRotateReg, [SiFiveP800IntArith]>;
+def : WriteRes<WriteRotateReg32, [SiFiveP800IntArith]>;
+
+def : WriteRes<WriteCLZ, [SiFiveP800IntArith]>;
+def : WriteRes<WriteCLZ32, [SiFiveP800IntArith]>;
+def : WriteRes<WriteCTZ, [SiFiveP800IntArith]>;
+def : WriteRes<WriteCTZ32, [SiFiveP800IntArith]>;
+
+def : WriteRes<WriteORCB, [SiFiveP800IntArith]>;
+def : WriteRes<WriteIMinMax, [SiFiveP800IntArith]>;
+
+def : WriteRes<WriteREV8, [SiFiveP800IntArith]>;
+
+def : WriteRes<WriteSHXADD, [SiFiveP800IntArith]>;
+def : WriteRes<WriteSHXADD32, [SiFiveP800IntArith]>;
+
+def : WriteRes<WriteSingleBit, [SiFiveP800IntArith]>;
+def : WriteRes<WriteSingleBitImm, [SiFiveP800IntArith]>;
+def : WriteRes<WriteBEXT, [SiFiveP800IntArith]>;
+def : WriteRes<WriteBEXTI, [SiFiveP800IntArith]>;
+
+// Memory
+def : WriteRes<WriteSTB, [SiFiveP800LDST]>;
+def : WriteRes<WriteSTH, [SiFiveP800LDST]>;
+def : WriteRes<WriteSTW, [SiFiveP800LDST]>;
+def : WriteRes<WriteSTD, [SiFiveP800LDST]>;
+def : WriteRes<WriteFST16, [SiFiveP800LDST]>;
+def : WriteRes<WriteFST32, [SiFiveP800LDST]>;
+def : WriteRes<WriteFST64, [SiFiveP800LDST]>;
+
+let Latency = 4 in {
+def : WriteRes<WriteLDB, [SiFiveP800Load]>;
+def : WriteRes<WriteLDH, [SiFiveP800Load]>;
+}
+let Latency = 4 in {
+def : WriteRes<WriteLDW, [SiFiveP800Load]>;
+def : WriteRes<WriteLDD, [SiFiveP800Load]>;
+}
+
+let Latency = 5 in {
+def : WriteRes<WriteFLD16, [SiFiveP800Load]>;
+def : WriteRes<WriteFLD32, [SiFiveP800Load]>;
+def : WriteRes<WriteFLD64, [SiFiveP800Load]>;
+}
+
+// Atomic memory
+let Latency = 3 in {
+def : WriteRes<WriteAtomicSTW, [SiFiveP800LDST]>;
+def : WriteRes<WriteAtomicSTD, [SiFiveP800LDST]>;
+def : WriteRes<WriteAtomicW, [SiFiveP800LDST]>;
+def : WriteRes<WriteAtomicD, [SiFiveP800LDST]>;
+def : WriteRes<WriteAtomicLDW, [SiFiveP800Load]>;
+def : WriteRes<WriteAtomicLDD, [SiFiveP800Load]>;
+}
+
+// Floating point
+let Latency = 2 in {
+def : WriteRes<WriteFAdd16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFAdd32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFAdd64, [SiFiveP800FloatArith]>;
+}
+let Latency = 3 in {
+def : WriteRes<WriteFMul16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMul32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMul64, [SiFiveP800FloatArith]>;
+}
+let Latency = 4 in {
+def : WriteRes<WriteFMA16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMA32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMA64, [SiFiveP800FloatArith]>;
+}
+
+let Latency = 2 in {
+def : WriteRes<WriteFSGNJ16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFSGNJ32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFSGNJ64, [SiFiveP800FloatArith]>;
+
+def : WriteRes<WriteFMinMax16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMinMax32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFMinMax64, [SiFiveP800FloatArith]>;
+}
+
+// Half precision.
+def : WriteRes<WriteFDiv16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1, 4];
+}
+def : WriteRes<WriteFSqrt16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 18;
+ let ReleaseAtCycles = [1, 17];
+}
+
+// Single precision.
+def : WriteRes<WriteFDiv32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 6;
+ let ReleaseAtCycles = [1, 6];
+}
+def : WriteRes<WriteFSqrt32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 18;
+ let ReleaseAtCycles = [1, 17];
+}
+
+// Double precision
+def : WriteRes<WriteFDiv64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 11;
+ let ReleaseAtCycles = [1, 11];
+}
+def : WriteRes<WriteFSqrt64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
+ let Latency = 33;
+ let ReleaseAtCycles = [1, 32];
+}
+
+// Conversions
+let Latency = 2 in {
+def : WriteRes<WriteFCvtI32ToF16, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtI32ToF32, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtI32ToF64, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtI64ToF16, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtI64ToF32, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtI64ToF64, [SiFiveP800I2F]>;
+def : WriteRes<WriteFCvtF16ToI32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF16ToI64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF16ToF32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFCvtF16ToF64, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFCvtF32ToI32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF32ToI64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF32ToF16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFCvtF32ToF64, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFCvtF64ToI32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF64ToI64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCvtF64ToF16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFCvtF64ToF32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFRoundF16, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFRoundF32, [SiFiveP800FloatArith]>;
+def : WriteRes<WriteFRoundF64, [SiFiveP800FloatArith]>;
+
+def : WriteRes<WriteFClass16, [SiFiveP800F2I]>;
+def : WriteRes<WriteFClass32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFClass64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCmp16, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCmp32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFCmp64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFMovI16ToF16, [SiFiveP800I2F]>;
+def : WriteRes<WriteFMovF16ToI16, [SiFiveP800F2I]>;
+def : WriteRes<WriteFMovI32ToF32, [SiFiveP800I2F]>;
+def : WriteRes<WriteFMovF32ToI32, [SiFiveP800F2I]>;
+def : WriteRes<WriteFMovI64ToF64, [SiFiveP800I2F]>;
+def : WriteRes<WriteFMovF64ToI64, [SiFiveP800F2I]>;
+def : WriteRes<WriteFLI16, [SiFiveP800I2F]>;
+def : WriteRes<WriteFLI32, [SiFiveP800I2F]>;
+def : WriteRes<WriteFLI64, [SiFiveP800I2F]>;
+}
+
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [SiFiveP800SYS]>;
+def : WriteRes<WriteVSETIVLI, [SiFiveP800SYS]>;
+def : WriteRes<WriteVSETVL, [SiFiveP800SYS]>;
+
+// 7. Vector Loads and Stores
+// FIXME: This unit is still being improved, currently
+// it is based on stage numbers. Estimates are optimistic,
+// latency may be longer.
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 8, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP800VLD], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP800VLD], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP800VLD], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 8, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP800VST], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP800VST], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP800VST], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar LMulLat = SiFiveP800GetCyclesSegmented<mx, eew>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFiveP800VLD], mx, IsWorstCase>;
+ }
+ let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFiveP800VST], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// Whole register move/load/store
+foreach LMul = [1, 2, 4, 8] in {
+ let Latency = 8, ReleaseAtCycles = [LMul] in {
+ def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP800VLD]>;
+ def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP800VST]>;
+ }
+ let Latency = 2, ReleaseAtCycles = [LMul] in {
+ def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP800VectorArith]>;
+ }
+}
+
+// 11. Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVExtV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+// Widening
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+
+// Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ defvar DivMicroOpLat =
+ !cond(!eq(sew, 8): 51, !eq(sew, 16): 45, !eq(sew, 32): 42,
+ /* SEW=64 */ true: 72);
+ defvar DivLatency = !mul(DivMicroOpLat, LMulLat);
+ let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP800VEXQ1, SiFiveP800VDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP800VEXQ1, SiFiveP800VDiv], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Narrowing Shift and Clips
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+
+// 13. Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVFClassV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListFW>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ }
+ }
+}
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP800VectorArith], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ defvar DivMicroOpLat =
+ !cond(!eq(sew, 16): 29, !eq(sew, 32): 25, /* SEW=64 */ true: 37);
+ defvar DivLatency = !mul(DivMicroOpLat, LMulLat);
+ let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP800VEXQ1, SiFiveP800VFloatDiv], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 14. Vector Reduction Operations
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+ let Latency = !add(2, !mul(2, LMulLat)), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",
+ [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
+ let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP800VEXQ1],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 15. Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// 16. Vector Permutation Instructions
+// Simple Slide
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+}
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// Complex Slide
+foreach mx = ["M8", "M4", "M2"] in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(4, LMulLat), ReleaseAtCycles = [LMulLat] in {
+ // TODO: The latencies and RThroughput for VISlideUpX and VISlideDownX are likely
+ // to be different in non-trivial LMUL. Update to the correct numbers here.
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP800VEXQ1], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP800VEXQ1], mx, IsWorstCase>;
+ }
+}
+
+let Latency = 2, ReleaseAtCycles = [1] in {
+ def : WriteRes<WriteVMovXS, [SiFiveP800VectorArith]>;
+ def : WriteRes<WriteVMovSX, [SiFiveP800VectorArith]>;
+}
+let Latency = 6, ReleaseAtCycles = [1] in {
+ def : WriteRes<WriteVMovFS, [SiFiveP800VectorArith]>;
+ def : WriteRes<WriteVMovSF, [SiFiveP800VectorArith]>;
+}
+
+// Simple Gather and Compress
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP800VEXQ1], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [1] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Complex Gather and Compress
+foreach mx = ["M2", "M4", "M8"] in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP800VEXQ1], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = ["M2", "M4", "M8"] in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP800VEXQ1], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Simple Vrgather.vi
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP800VEXQ1], mx, IsWorstCase>;
+ }
+}
+
+// Vector Crypto
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
+ // Zvbb
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ // Zvbc
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ // Zvkb
+ // VANDN uses WriteVIALU[V|X|I]
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ // Zvkg
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ // ZvknhaOrZvknhb
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defvar ZvknhSEWs = !listremove(SchedSEWSet<mx>.val, [8, 16]);
+ // Largest SEW is the last element, assuming SchedSEWSet is sorted in ascending
+ // order.
+ defvar LargestZvknhSEW = !foldl(!head(ZvknhSEWs), ZvknhSEWs, last, curr, curr);
+ foreach sew = ZvknhSEWs in {
+ // The worst case for Zvknh[ab] is designated to the largest SEW and LMUL.
+ defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, LargestZvknhSEW));
+ defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SiFiveP800VEXQ0], mx, sew,
+ IsWorstCaseVSHA2MSV>;
+ }
+ }
+ // Zvkned
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP800VectorArith], mx, IsWorstCase>;
+ }
+ // Zvksed
+ let Latency = 3, ReleaseAtCycles = [SiFiveP800VSM3CCycles<mx>.c] in
+ defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// Others
+def : WriteRes<WriteCSR, [SiFiveP800SYS]>;
+def : WriteRes<WriteNop, []>;
+def : WriteRes<WriteRdVLENB, [SiFiveP800SYS]>;
+
+// FIXME: This could be better modeled by looking at the regclasses of the operands.
+def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+// Bypass and advance
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShiftImm, 0>;
+def : ReadAdvance<ReadShiftImm32, 0>;
+def : ReadAdvance<ReadShiftReg, 0>;
+def : ReadAdvance<ReadShiftReg32, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
+def : ReadAdvance<ReadFMA16Addend, 2, [WriteFMA16]>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 2, [WriteFMA32]>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 2, [WriteFMA64]>;
+def : ReadAdvance<ReadFDiv16, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+def : ReadAdvance<ReadFRoundF16, 0>;
+def : ReadAdvance<ReadFRoundF32, 0>;
+def : ReadAdvance<ReadFRoundF64, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+// Bitmanip
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+def : ReadAdvance<ReadSingleBit, 0>;
+def : ReadAdvance<ReadSingleBitImm, 0>;
+
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 12. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 13. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 14. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// 15. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 16. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 17. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Vector Crypto Extensions
+// Zvbb
+defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
+defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
+defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
+// Zvbc
+defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
+// Zvkb
+// VANDN uses ReadVIALU[V|X|I]
+defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVRotV", 0>;
+defm "" : LMULReadAdvance<"ReadVRotX", 0>;
+// Zvkg
+defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
+defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
+// Zvknha or Zvknhb
+defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
+defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;
+// Zvkned
+defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
+// Zvksed
+defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
+// Zbksh
+defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedZbc;
+defm : UnsupportedSchedZbkb;
+defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedXsfvcp;
+}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/div.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/div.s
new file mode 100644
index 0000000000000..0eaf0b240b984
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/div.s
@@ -0,0 +1,854 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m8, tu, mu
+vdiv.vv v8, v16, v24
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m8, tu, mu
+vdiv.vx v8, v16, a0
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m8, tu, mu
+vfdiv.vv v8, v16, v24
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vfsqrt.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP800VDiv[102],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP800VDiv[204],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP800VDiv[408],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP800VDiv[90],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP800VDiv[180],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP800VDiv[360],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP800VDiv[84],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP800VDiv[168],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP800VDiv[336],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP800VDiv[72],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP800VDiv[72],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP800VDiv[144],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP800VDiv[288],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP800VDiv[576],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 51 51.00 51 SiFiveP800VDiv[51],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 102 102.00 102 SiFiveP800VDiv[102],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 204 SiFiveP800VDiv[204],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 408 408.00 408 SiFiveP800VDiv[408],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 45 45.00 45 SiFiveP800VDiv[45],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 90 90.00 90 SiFiveP800VDiv[90],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 180 180.00 180 SiFiveP800VDiv[180],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 360 360.00 360 SiFiveP800VDiv[360],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 42 42.00 42 SiFiveP800VDiv[42],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 84 84.00 84 SiFiveP800VDiv[84],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 168 168.00 168 SiFiveP800VDiv[168],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 336 336.00 336 SiFiveP800VDiv[336],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP800VDiv[72],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SiFiveP800VDiv[72],SiFiveP800VEXQ1,SiFiveP800VectorArith VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SiFiveP800VDiv[144],SiFiveP800VEXQ1[2],SiFiveP800VectorArith[2] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SiFiveP800VDiv[288],SiFiveP800VEXQ1[4],SiFiveP800VectorArith[4] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 576 576.00 576 SiFiveP800VDiv[576],SiFiveP800VEXQ1[8],SiFiveP800VectorArith[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[58],SiFiveP800VectorArith[2] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[116],SiFiveP800VectorArith[4] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[50],SiFiveP800VectorArith[2] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[100],SiFiveP800VectorArith[4] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[200],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[74],SiFiveP800VectorArith[2] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[148],SiFiveP800VectorArith[4] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[296],SiFiveP800VectorArith[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[58],SiFiveP800VectorArith[2] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[116],SiFiveP800VectorArith[4] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[50],SiFiveP800VectorArith[2] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[100],SiFiveP800VectorArith[4] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[200],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[74],SiFiveP800VectorArith[2] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[148],SiFiveP800VectorArith[4] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[296],SiFiveP800VectorArith[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 29 29.00 29 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[29],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 58 58.00 58 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[58],SiFiveP800VectorArith[2] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 116 116.00 116 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[116],SiFiveP800VectorArith[4] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 232 232.00 232 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[232],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 25.00 25 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[25],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 50 50.00 50 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[50],SiFiveP800VectorArith[2] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 100 100.00 100 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[100],SiFiveP800VectorArith[4] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 200 200.00 200 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[200],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 37 37.00 37 SiFiveP800VEXQ1,SiFiveP800VFloatDiv[37],SiFiveP800VectorArith VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 74 74.00 74 SiFiveP800VEXQ1[2],SiFiveP800VFloatDiv[74],SiFiveP800VectorArith[2] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 148 148.00 148 SiFiveP800VEXQ1[4],SiFiveP800VFloatDiv[148],SiFiveP800VectorArith[4] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 296 296.00 296 SiFiveP800VEXQ1[8],SiFiveP800VFloatDiv[296],SiFiveP800VectorArith[8] VFSQRT_V vfsqrt.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 130.00 - - - - - - - 7290.00 - 485.00 10185.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 51.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 102.00 - 2.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 204.00 - 4.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 408.00 - 8.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 45.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 45.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 45.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 45.00 - 1.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 90.00 - 2.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - 180.00 - 4.00 - - - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 296.00 - - vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 29.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 58.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 116.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 232.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 25.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 50.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 100.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 200.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 37.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 74.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 4.00 148.00 - - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - 8.00 296.00 - - vfsqrt.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/fmadd.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/fmadd.s
new file mode 100644
index 0000000000000..519f3700d0589
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/fmadd.s
@@ -0,0 +1,199 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+# COM: Check if we're only bypassing on rs3 of FMADD (i.e. addend) or not.
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -timeline < %s | FileCheck %s --check-prefix=TIMELINE
+
+fmadd.s fa0, fa0, fa1, fa2
+fmadd.s fa2, fa2, fa1, fa0
+fmadd.s ft1, ft1, fa2, ft0
+
+fmadd.d fa0, fa0, fa1, fa2
+fmadd.d fa2, fa2, fa1, fa0
+fmadd.d ft1, ft1, fa2, ft0
+
+fmadd.h fa0, fa0, fa1, fa2
+fmadd.h fa2, fa2, fa1, fa0
+fmadd.h ft1, ft1, fa2, ft0
+
+# TIMELINE: Iterations: 1
+# TIMELINE-NEXT: Instructions: 9
+# TIMELINE-NEXT: Total Cycles: 25
+# TIMELINE-NEXT: Total uOps: 9
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# TIMELINE: Dispatch Width: 6
+# TIMELINE-NEXT: uOps Per Cycle: 0.36
+# TIMELINE-NEXT: IPC: 0.36
+# TIMELINE-NEXT: Block RThroughput: 4.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# TIMELINE: Instruction Info:
+# TIMELINE-NEXT: [1]: #uOps
+# TIMELINE-NEXT: [2]: Latency
+# TIMELINE-NEXT: [3]: RThroughput
+# TIMELINE-NEXT: [4]: MayLoad
+# TIMELINE-NEXT: [5]: MayStore
+# TIMELINE-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s fa0, fa0, fa1, fa2
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s fa2, fa2, fa1, fa0
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_S fmadd.s ft1, ft1, fa2, ft0
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d fa0, fa0, fa1, fa2
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d fa2, fa2, fa1, fa0
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_D fmadd.d ft1, ft1, fa2, ft0
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h fa0, fa0, fa1, fa2
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h fa2, fa2, fa1, fa0
+# CHECK-NEXT: 1 4 0.50 2 SiFiveP800FloatArith FMADD_H fmadd.h ft1, ft1, fa2, ft0
+
+# TIMELINE: [1] [2] [3] [4] [5] [6] Instructions:
+# TIMELINE-NEXT: 1 4 0.50 fmadd.s fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 1 4 0.50 fmadd.s fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 1 4 0.50 fmadd.s ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: 1 4 0.50 fmadd.d fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 1 4 0.50 fmadd.d fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 1 4 0.50 fmadd.d ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: 1 4 0.50 fmadd.h fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 1 4 0.50 fmadd.h fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 1 4 0.50 fmadd.h ft1, ft1, fa2, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# TIMELINE: Resources:
+# TIMELINE-NEXT: [0] - SiFiveP800Div
+# TIMELINE-NEXT: [1] - SiFiveP800FEXQ0
+# TIMELINE-NEXT: [2] - SiFiveP800FEXQ1
+# TIMELINE-NEXT: [3] - SiFiveP800FloatDiv
+# TIMELINE-NEXT: [4] - SiFiveP800IEXQ0
+# TIMELINE-NEXT: [5] - SiFiveP800IEXQ1
+# TIMELINE-NEXT: [6] - SiFiveP800IEXQ2
+# TIMELINE-NEXT: [7] - SiFiveP800IEXQ3
+# TIMELINE-NEXT: [8] - SiFiveP800IEXQ4
+# TIMELINE-NEXT: [9] - SiFiveP800IEXQ5
+# TIMELINE-NEXT: [10] - SiFiveP800LD
+# TIMELINE-NEXT: [11.0] - SiFiveP800LDST
+# TIMELINE-NEXT: [11.1] - SiFiveP800LDST
+# TIMELINE-NEXT: [12] - SiFiveP800VDiv
+# TIMELINE-NEXT: [13] - SiFiveP800VEXQ0
+# TIMELINE-NEXT: [14] - SiFiveP800VEXQ1
+# TIMELINE-NEXT: [15] - SiFiveP800VFloatDiv
+# TIMELINE-NEXT: [16] - SiFiveP800VLD
+# TIMELINE-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - 4.50 4.50 - - - - - - - - - - - - - - - -
+
+# TIMELINE: Resource pressure per iteration:
+# TIMELINE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# TIMELINE-NEXT: - 4.00 5.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s fa0, fa0, fa1, fa2
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s fa2, fa2, fa1, fa0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.s ft1, ft1, fa2, ft0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d fa0, fa0, fa1, fa2
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d fa2, fa2, fa1, fa0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.d ft1, ft1, fa2, ft0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h fa0, fa0, fa1, fa2
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h fa2, fa2, fa1, fa0
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fmadd.h ft1, ft1, fa2, ft0
+
+# TIMELINE: Resource pressure by instruction:
+# TIMELINE-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.s fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.s fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.s ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.d fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.d fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.d ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.h fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: - 1.00 - - - - - - - - - - - - - - - - - fmadd.h fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: - - 1.00 - - - - - - - - - - - - - - - - fmadd.h ft1, ft1, fa2, ft0
+
+# TIMELINE: Timeline view:
+# TIMELINE-NEXT: 0123456789
+# TIMELINE-NEXT: Index 0123456789 01234
+
+# TIMELINE: [0,0] DeeeeER . . . . fmadd.s fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: [0,1] D==eeeeER . . . . fmadd.s fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: [0,2] D======eeeeER . . . fmadd.s ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: [0,3] D======eeeeER . . . fmadd.d fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: [0,4] D========eeeeER. . . fmadd.d fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: [0,5] D============eeeeER . . fmadd.d ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: [0,6] .D===========eeeeER . . fmadd.h fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: [0,7] .D=============eeeeER . fmadd.h fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: [0,8] .D=================eeeeER fmadd.h ft1, ft1, fa2, ft0
+
+# TIMELINE: Average Wait times (based on the timeline view):
+# TIMELINE-NEXT: [0]: Executions
+# TIMELINE-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# TIMELINE-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# TIMELINE-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# TIMELINE: [0] [1] [2] [3]
+# TIMELINE-NEXT: 0. 1 1.0 1.0 0.0 fmadd.s fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 1. 1 3.0 0.0 0.0 fmadd.s fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 2. 1 7.0 0.0 0.0 fmadd.s ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: 3. 1 7.0 0.0 0.0 fmadd.d fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 4. 1 9.0 0.0 0.0 fmadd.d fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 5. 1 13.0 0.0 0.0 fmadd.d ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: 6. 1 12.0 0.0 0.0 fmadd.h fa0, fa0, fa1, fa2
+# TIMELINE-NEXT: 7. 1 14.0 0.0 0.0 fmadd.h fa2, fa2, fa1, fa0
+# TIMELINE-NEXT: 8. 1 18.0 0.0 0.0 fmadd.h ft1, ft1, fa2, ft0
+# TIMELINE-NEXT: 1 9.3 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/load.s
new file mode 100644
index 0000000000000..8e7e88f51b217
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/load.s
@@ -0,0 +1,86 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+lw t0, 0(a0)
+ld t0, 0(a0)
+
+flh ft0, 0(a0)
+flw ft0, 0(a0)
+fld ft0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 SiFiveP800Load LD ld t0, 0(a0)
+# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 5 0.33 * 5 SiFiveP800Load FLD fld ft0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - - - - - - 1.67 1.67 1.67 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - 0.33 0.33 0.33 - - - - - - fld ft0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mask.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mask.s
new file mode 100644
index 0000000000000..c6e3e91e852ca
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mask.s
@@ -0,0 +1,151 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, ta, ma
+
+vmslt.vv v0, v4, v20
+vmsle.vv v8, v4, v20
+vmsgt.vv v8, v20, v4
+vmsge.vv v8, v20, v4
+vmseq.vv v8, v4, v20
+vmsne.vv v8, v4, v20
+vmsltu.vv v8, v4, v20
+vmsleu.vv v8, v4, v20
+vmsgtu.vv v8, v20, v4
+vmsgeu.vv v8, v20, v4
+
+vmflt.vv v0, v4, v20
+vmfle.vv v8, v4, v20
+vmfgt.vv v8, v20, v4
+vmfge.vv v8, v20, v4
+vmfeq.vv v8, v4, v20
+vmfne.vv v8, v4, v20
+
+vmadc.vv v8, v4, v20
+vmsbc.vv v8, v4, v20
+
+vfirst.m a2, v4
+vpopc.m a2, v4
+
+viota.m v8, v4
+
+vmsbf.m v8, v4
+vmsif.m v8, v4
+vmsof.m v8, v4
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLT_VV vmslt.vv v0, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLE_VV vmsle.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLT_VV vmslt.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLE_VV vmsle.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSEQ_VV vmseq.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSNE_VV vmsne.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLTU_VV vmsltu.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLEU_VV vmsleu.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLTU_VV vmsltu.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSLEU_VV vmsleu.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLT_VV vmflt.vv v0, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLE_VV vmfle.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLT_VV vmflt.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFLE_VV vmfle.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFEQ_VV vmfeq.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMFNE_VV vmfne.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMADC_VV vmadc.vv v8, v4, v20
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMSBC_VV vmsbc.vv v8, v4, v20
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VFIRST_M vfirst.m a2, v4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VCPOP_M vcpop.m a2, v4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VIOTA_M viota.m v8, v4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSBF_M vmsbf.m v8, v4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSIF_M vmsif.m v8, v4
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VEXQ0,SiFiveP800VectorArith VMSOF_M vmsof.m v8, v4
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - 15.00 9.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmslt.vv v0, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsle.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmslt.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsle.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmseq.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsne.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsltu.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsleu.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsltu.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsleu.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmflt.vv v0, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfle.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmflt.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfle.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfeq.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmfne.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmadc.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmsbc.vv v8, v4, v20
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vfirst.m a2, v4
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vcpop.m a2, v4
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - viota.m v8, v4
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsbf.m v8, v4
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsif.m v8, v4
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vmsof.m v8, v4
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-cpop.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-cpop.s
new file mode 100644
index 0000000000000..748493e91eed5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-cpop.s
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+mul s6, s6, s7
+
+mulw s4, s4, a2
+
+cpop t1, t1
+
+cpopw t2, t2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul MUL mul s6, s6, s7
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul MULW mulw s4, s4, a2
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul CPOP cpop t1, t1
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800IntArith,SiFiveP800Mul CPOPW cpopw t2, t2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 2.00 - 2.00 - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - mul s6, s6, s7
+# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - mulw s4, s4, a2
+# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - cpop t1, t1
+# CHECK-NEXT: - - - - - 0.50 - 0.50 - - - - - - - - - - - cpopw t2, t2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s
new file mode 100644
index 0000000000000..ca41121ccbfad
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vle-vse-vlm.s
@@ -0,0 +1,567 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VST[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VST[4] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VST[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VST[4] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VST[2] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VST[4] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VST VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VST[2] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VST[4] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VST[8] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 8 1.00 * 8 SiFiveP800VLD VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 2.00 * 8 SiFiveP800VLD[2] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 4.00 * 8 SiFiveP800VLD[4] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SiFiveP800VLD[8] VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 80.00 - - - - - - - - - - - 188.00 122.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlse-vsse.s
new file mode 100644
index 0000000000000..494b76241d05b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlse-vsse.s
@@ -0,0 +1,341 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 44.00 - - - - - - - - - - - 66.00 66.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s
new file mode 100644
index 0000000000000..b965e98193de9
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlseg-vsseg.s
@@ -0,0 +1,4752 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+
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+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsuxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsuxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsuxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsuxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsuxseg8ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m4, tu, mu
+vsoxseg2ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m4, tu, mu
+vsoxseg2ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m4, tu, mu
+vsoxseg2ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m4, tu, mu
+vsoxseg2ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg3ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg3ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg3ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg3ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg3ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg4ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg4ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg4ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg4ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg4ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg5ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg5ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg5ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg5ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg6ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg6ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP800VLD[76] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP800VST[76] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP800VLD[76] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP800VST[76] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP800VLD[76] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP800VLD[76] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * 76 SiFiveP800VLD[76] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * 44 SiFiveP800VLD[44] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SiFiveP800VLD[28] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SiFiveP800VLD[20] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SiFiveP800VLD[16] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 * 14 SiFiveP800VLD[14] VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * 65 SiFiveP800VST[76] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * 33 SiFiveP800VST[44] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * 17 SiFiveP800VST[28] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * 9 SiFiveP800VST[20] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * 5 SiFiveP800VST[16] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 14.00 * 3 SiFiveP800VST[14] VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 770.00 - - - - - - - - - - - 8480.00 6616.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 44.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 76.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 44.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 44.00 - vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 44.00 - vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg4e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg4e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg5e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg5e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg5e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg5e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg5e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg6e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg6e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg6e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg6e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg6e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg6e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg6e16.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg6e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg6e32.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg6e64.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg7e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 16.00 - vlseg7e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 20.00 - vlseg7e8.v v8, (a0)
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 28.00 - vlseg7e8.v v8, (a0)
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+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 14.00 - vlseg7e16.v v8, (a0)
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+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 16.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 14.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s
new file mode 100644
index 0000000000000..9fb98e2c5a4d1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vlxe-vsxe.s
@@ -0,0 +1,613 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VLD VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VLD[2] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VLD[4] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VLD[8] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 12 1.00 * 12 SiFiveP800VST VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 12 2.00 * 12 SiFiveP800VST[2] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 12 4.00 * 12 SiFiveP800VST[4] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 12 8.00 * 12 SiFiveP800VST[8] VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 88.00 - - - - - - - - - - - 132.00 132.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 2.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 4.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 8.00 - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vmv.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vmv.s
new file mode 100644
index 0000000000000..b5b2ff2939551
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/vmv.s
@@ -0,0 +1,694 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv8r.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VMV8R_V vmv8r.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 104.00 - - - - - - - - 195.00 195.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vmv8r.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s
new file mode 100644
index 0000000000000..2bc5cc197be95
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s
@@ -0,0 +1,98 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+fli.h fa5, nan
+fli.s fa5, nan
+fli.d fa5, nan
+
+fround.h fa0, fa0, rdn
+froundnx.h fa0, fa0, rdn
+fround.s fa0, fa0, rdn
+froundnx.s fa0, fa0, rdn
+fround.d fa0, fa0, rdn
+froundnx.d fa0, fa0, rdn
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800IEXQ3,SiFiveP800IntArith,SiFiveP800Mul FLI_H fli.h fa5, nan
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800IEXQ3,SiFiveP800IntArith,SiFiveP800Mul FLI_S fli.s fa5, nan
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800IEXQ3,SiFiveP800IntArith,SiFiveP800Mul FLI_D fli.d fa5, nan
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUND_H fround.h fa0, fa0, rdn
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUNDNX_H froundnx.h fa0, fa0, rdn
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUND_S fround.s fa0, fa0, rdn
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUNDNX_S froundnx.s fa0, fa0, rdn
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUND_D fround.d fa0, fa0, rdn
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800FloatArith FROUNDNX_D froundnx.d fa0, fa0, rdn
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - 3.00 3.00 - - - - 3.00 - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - fli.h fa5, nan
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - fli.s fa5, nan
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - fli.d fa5, nan
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fround.h fa0, fa0, rdn
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - froundnx.h fa0, fa0, rdn
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fround.s fa0, fa0, rdn
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - froundnx.s fa0, fa0, rdn
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - fround.d fa0, fa0, rdn
+# CHECK-NEXT: - 0.50 0.50 - - - - - - - - - - - - - - - - froundnx.d fa0, fa0, rdn
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbb.s
new file mode 100644
index 0000000000000..a2cf112b09e3c
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbb.s
@@ -0,0 +1,483 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vandn.vv v8, v16, v24
+vandn.vx v8, v16, a0
+vbrev.v v8, v16
+vbrev8.v v8, v16
+vrev8.v v8, v16
+vclz.v v8, v16
+vctz.v v8, v16
+vcpop.v v8, v16
+vrol.vv v8, v16, v24
+vrol.vx v8, v16, a0
+vror.vv v8, v16, v24
+vror.vx v8, v16, a0
+vror.vi v8, v16, 8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VV vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VX vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VI vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VV vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VX vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VI vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VV vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VX vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VI vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VV vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VX vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VWSLL_VI vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VWSLL_VV vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VWSLL_VX vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VWSLL_VI vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VV vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VX vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VI vwsll.vi v8, v4, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VANDN_VV vandn.vv v8, v16, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VANDN_VX vandn.vx v8, v16, a0
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VBREV_V vbrev.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VBREV8_V vbrev8.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VREV8_V vrev8.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLZ_V vclz.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCTZ_V vctz.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCPOP_V vcpop.v v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VROL_VV vrol.vv v8, v16, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VROL_VX vrol.vx v8, v16, a0
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VROR_VV vror.vv v8, v16, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VROR_VX vror.vx v8, v16, a0
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VROR_VI vror.vi v8, v16, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VANDN_VV vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VANDN_VX vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VBREV_V vbrev.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VBREV8_V vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VREV8_V vrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLZ_V vclz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCTZ_V vctz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCPOP_V vcpop.v v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROL_VV vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROL_VX vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VV vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VX vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VROR_VI vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VV vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VX vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VWSLL_VI vwsll.vi v8, v4, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 8.00 - - - - - - - - 164.00 164.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vi v8, v4, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vandn.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vandn.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vbrev.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vbrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vctz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vcpop.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vrol.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vrol.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vror.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vror.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vror.vi v8, v16, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vwsll.vi v8, v4, 8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbc.s
new file mode 100644
index 0000000000000..a0ace32cc4eaf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvbc.s
@@ -0,0 +1,135 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# These instructions only work with e64
+
+vsetvli zero, zero, e64, m1, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m8, tu, mu
+vclmul.vv v8, v12, v24
+vclmul.vx v8, v12, a0
+vclmulh.vv v8, v12, v24
+vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMUL_VV vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMUL_VX vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMULH_VV vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VCLMULH_VX vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMUL_VV vclmul.vv v8, v12, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMUL_VX vclmul.vx v8, v12, a0
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMULH_VV vclmulh.vv v8, v12, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VCLMULH_VX vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 4.00 - - - - - - - - 30.00 30.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmul.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmul.vx v8, v12, a0
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmulh.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vclmulh.vx v8, v12, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkg.s
new file mode 100644
index 0000000000000..ae2880e4c8697
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkg.s
@@ -0,0 +1,150 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vghsh.vv v8, v16, v24
+vgmul.vv v8, v16
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGMUL_VV vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGHSH_VV vghsh.vv v8, v16, v24
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VGMUL_VV vgmul.vv v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGHSH_VV vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VGMUL_VV vgmul.vv v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 8.00 - - - - - - - - 36.00 36.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vghsh.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vgmul.vv v8, v16
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vgmul.vv v4, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkned.s
new file mode 100644
index 0000000000000..c0c935e855b73
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvkned.s
@@ -0,0 +1,226 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vaesef.vv v8, v16
+vaesef.vs v8, v16
+vaesem.vv v8, v16
+vaesem.vs v8, v16
+vaesdm.vv v8, v16
+vaesdm.vs v8, v16
+vaeskf1.vi v8, v16, 8
+vaeskf2.vi v8, v16, 8
+vaesz.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VV vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VS vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VV vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VS vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VV vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VS vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF1_VI vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF2_VI vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESZ_VS vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VV vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEF_VS vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VV vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESEM_VS vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VV vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESDM_VS vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF1_VI vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESKF2_VI vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 0.50 2 SiFiveP800VectorArith VAESZ_VS vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEF_VV vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEF_VS vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEM_VV vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESEM_VS vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESDM_VV vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESDM_VS vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESKF1_VI vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESKF2_VI vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 2 SiFiveP800VectorArith[2] VAESZ_VS vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEF_VV vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEF_VS vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEM_VV vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESEM_VS vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESDM_VV vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESDM_VS vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESKF1_VI vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESKF2_VI vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 2 SiFiveP800VectorArith[4] VAESZ_VS vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEF_VV vaesef.vv v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEF_VS vaesef.vs v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEM_VV vaesem.vv v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESEM_VS vaesem.vs v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESDM_VV vaesdm.vv v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESDM_VS vaesdm.vs v8, v16
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESKF1_VI vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESKF2_VI vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: 1 2 4.00 2 SiFiveP800VectorArith[8] VAESZ_VS vaesz.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 5.00 - - - - - - - - 72.00 72.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesef.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesef.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesem.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesem.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesdm.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesdm.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - - vaesz.vs v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s
new file mode 100644
index 0000000000000..fa9c9f6f4e680
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvknhb.s
@@ -0,0 +1,180 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# Worst case for vsha2ms should be that of LMUL=8 and SEW=64.
+vsha2ms.vv v4, v8, v12
+
+# SEW is only e32 or e64
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+vsetvli zero, zero, e64, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CH_VV vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CL_VV vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2MS_VV vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CH_VV vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSHA2CL_VV vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2MS_VV vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CH_VV vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSHA2CL_VV vsha2cl.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 8.00 - - - - - - - - 98.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksed.s
new file mode 100644
index 0000000000000..392c6efa82db7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksed.s
@@ -0,0 +1,136 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm4k.vi v8, v16, 8
+vsm4r.vv v8, v16
+vsm4r.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4K_VI vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VV vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VS vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4K_VI vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VV vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM4R_VS vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4K_VI vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4R_VV vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM4R_VS vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4K_VI vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4R_VV vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM4R_VS vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4K_VI vsm4k.vi v8, v16, 8
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4R_VV vsm4r.vv v8, v16
+# CHECK-NEXT: 1 3 8.00 3 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM4R_VS vsm4r.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 5.00 - - - - - - - - 48.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4k.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4r.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm4r.vs v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksh.s
new file mode 100644
index 0000000000000..9dc2aef567805
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zvksh.s
@@ -0,0 +1,121 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm3me.vv v8, v16, v24
+vsm3c.vi v8, v16, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5
+# CHECK-NEXT: [1] - SiFiveP800Div:1
+# CHECK-NEXT: [2] - SiFiveP800FEXQ0:1
+# CHECK-NEXT: [3] - SiFiveP800FEXQ1:1
+# CHECK-NEXT: [4] - SiFiveP800FloatArith:2 SiFiveP800FEXQ0, SiFiveP800FEXQ1
+# CHECK-NEXT: [5] - SiFiveP800FloatDiv:1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ0:1
+# CHECK-NEXT: [7] - SiFiveP800IEXQ1:1
+# CHECK-NEXT: [8] - SiFiveP800IEXQ2:1
+# CHECK-NEXT: [9] - SiFiveP800IEXQ3:1
+# CHECK-NEXT: [10] - SiFiveP800IEXQ4:1
+# CHECK-NEXT: [11] - SiFiveP800IEXQ5:1
+# CHECK-NEXT: [12] - SiFiveP800IntArith:4 SiFiveP800IEXQ0, SiFiveP800IEXQ1, SiFiveP800IEXQ2, SiFiveP800IEXQ3
+# CHECK-NEXT: [13] - SiFiveP800LD:1
+# CHECK-NEXT: [14] - SiFiveP800LDST:2
+# CHECK-NEXT: [15] - SiFiveP800Load:3 SiFiveP800LDST, SiFiveP800LDST, SiFiveP800LD
+# CHECK-NEXT: [16] - SiFiveP800Mul:2 SiFiveP800IEXQ1, SiFiveP800IEXQ3
+# CHECK-NEXT: [17] - SiFiveP800VDiv:1
+# CHECK-NEXT: [18] - SiFiveP800VEXQ0:1
+# CHECK-NEXT: [19] - SiFiveP800VEXQ1:1
+# CHECK-NEXT: [20] - SiFiveP800VFloatDiv:1
+# CHECK-NEXT: [21] - SiFiveP800VLD:1
+# CHECK-NEXT: [22] - SiFiveP800VST:1
+# CHECK-NEXT: [23] - SiFiveP800VectorArith:2 SiFiveP800VEXQ0, SiFiveP800VEXQ1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM3ME_VV vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM3C_VI vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM3ME_VV vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM3C_VI vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM3ME_VV vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 3 SiFiveP800VEXQ0,SiFiveP800VectorArith VSM3C_VI vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM3ME_VV vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 3 SiFiveP800VEXQ0[2],SiFiveP800VectorArith[2] VSM3C_VI vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U 1 SiFiveP800IEXQ1,SiFiveP800IntArith,SiFiveP800Mul VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 6 SiFiveP800VEXQ0[8],SiFiveP800VectorArith[8] VSM3ME_VV vsm3me.vv v8, v16, v24
+# CHECK-NEXT: 1 3 4.00 3 SiFiveP800VEXQ0[4],SiFiveP800VectorArith[4] VSM3C_VI vsm3c.vi v8, v16, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP800Div
+# CHECK-NEXT: [1] - SiFiveP800FEXQ0
+# CHECK-NEXT: [2] - SiFiveP800FEXQ1
+# CHECK-NEXT: [3] - SiFiveP800FloatDiv
+# CHECK-NEXT: [4] - SiFiveP800IEXQ0
+# CHECK-NEXT: [5] - SiFiveP800IEXQ1
+# CHECK-NEXT: [6] - SiFiveP800IEXQ2
+# CHECK-NEXT: [7] - SiFiveP800IEXQ3
+# CHECK-NEXT: [8] - SiFiveP800IEXQ4
+# CHECK-NEXT: [9] - SiFiveP800IEXQ5
+# CHECK-NEXT: [10] - SiFiveP800LD
+# CHECK-NEXT: [11.0] - SiFiveP800LDST
+# CHECK-NEXT: [11.1] - SiFiveP800LDST
+# CHECK-NEXT: [12] - SiFiveP800VDiv
+# CHECK-NEXT: [13] - SiFiveP800VEXQ0
+# CHECK-NEXT: [14] - SiFiveP800VEXQ1
+# CHECK-NEXT: [15] - SiFiveP800VFloatDiv
+# CHECK-NEXT: [16] - SiFiveP800VLD
+# CHECK-NEXT: [17] - SiFiveP800VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17]
+# CHECK-NEXT: - - - - - 5.00 - - - - - - - - 25.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11.0] [11.1] [12] [13] [14] [15] [16] [17] Instructions:
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - - vsm3me.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - - vsm3c.vi v8, v16, 8
>From a227b33681040dc52624b3eeabfbc9afbd84707b Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Tue, 13 May 2025 09:22:04 -0700
Subject: [PATCH 2/3] fixup! Remove the PostRAScheduler field
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index f226f1f683f5e..a645f8958665a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -63,7 +63,6 @@ def SiFiveP800Model : SchedMachineModel {
let MicroOpBufferSize = 288; // Max micro-ops that can be buffered.
let LoadLatency = 4; // Cycles for loads to access the cache.
let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
- let PostRAScheduler = true;
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
>From 988bb261b55ef9635ada83330447a57529533d09 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 16 May 2025 13:20:10 -0700
Subject: [PATCH 3/3] fixup! Update latency of atomic memory ops and FSqrt
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td | 20 ++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index a645f8958665a..c14c8888f6d55 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -198,8 +198,6 @@ def : WriteRes<WriteFST64, [SiFiveP800LDST]>;
let Latency = 4 in {
def : WriteRes<WriteLDB, [SiFiveP800Load]>;
def : WriteRes<WriteLDH, [SiFiveP800Load]>;
-}
-let Latency = 4 in {
def : WriteRes<WriteLDW, [SiFiveP800Load]>;
def : WriteRes<WriteLDD, [SiFiveP800Load]>;
}
@@ -211,11 +209,15 @@ def : WriteRes<WriteFLD64, [SiFiveP800Load]>;
}
// Atomic memory
-let Latency = 3 in {
def : WriteRes<WriteAtomicSTW, [SiFiveP800LDST]>;
def : WriteRes<WriteAtomicSTD, [SiFiveP800LDST]>;
+
+let Latency = 7 in {
def : WriteRes<WriteAtomicW, [SiFiveP800LDST]>;
def : WriteRes<WriteAtomicD, [SiFiveP800LDST]>;
+}
+
+let Latency = 10 in {
def : WriteRes<WriteAtomicLDW, [SiFiveP800Load]>;
def : WriteRes<WriteAtomicLDD, [SiFiveP800Load]>;
}
@@ -253,8 +255,8 @@ def : WriteRes<WriteFDiv16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
let ReleaseAtCycles = [1, 4];
}
def : WriteRes<WriteFSqrt16, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
- let Latency = 18;
- let ReleaseAtCycles = [1, 17];
+ let Latency = 8;
+ let ReleaseAtCycles = [1, 7];
}
// Single precision.
@@ -263,8 +265,8 @@ def : WriteRes<WriteFDiv32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
let ReleaseAtCycles = [1, 6];
}
def : WriteRes<WriteFSqrt32, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
- let Latency = 18;
- let ReleaseAtCycles = [1, 17];
+ let Latency = 14;
+ let ReleaseAtCycles = [1, 13];
}
// Double precision
@@ -273,8 +275,8 @@ def : WriteRes<WriteFDiv64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
let ReleaseAtCycles = [1, 11];
}
def : WriteRes<WriteFSqrt64, [SiFiveP800FEXQ1, SiFiveP800FloatDiv]> {
- let Latency = 33;
- let ReleaseAtCycles = [1, 32];
+ let Latency = 29;
+ let ReleaseAtCycles = [1, 28];
}
// Conversions
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