[llvm] [AMDGPU] Fix opsel for scaled MFMA operations (PR #140183)

[Vigneshwar Jayakumar via llvm-commits]

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@@ -526,14 +526,14 @@ class VOP3PXe <bits<7> op, VOPProfile MFMAPfl, bit acc_cd = 0> : Enc128, VOP3Pe_
   bits<9> scale_src0;
   bits<9> scale_src1;
 
-  bits<2> scale_src0_opsel;
-  bits<2> scale_src1_opsel;
+  bits<4> src0_modifiers;
+  bits<4> src1_modifiers;
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VigneshwarJ wrote:

Oh I see it,  I see this in doc " NEG[1:0] and ABS[1:0] must be zero. NEG[2] and ABS[2] may be used to control matrix C" . So I will wire up a src2_modifier with neg/abs bits mapped and add some tests for it as well

https://github.com/llvm/llvm-project/pull/140183