[llvm] [AMDGPU] Fix opsel for scaled MFMA operations (PR #140183)

[Vigneshwar Jayakumar via llvm-commits]

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@@ -526,14 +526,14 @@ class VOP3PXe <bits<7> op, VOPProfile MFMAPfl, bit acc_cd = 0> : Enc128, VOP3Pe_
   bits<9> scale_src0;
   bits<9> scale_src1;
 
-  bits<2> scale_src0_opsel;
-  bits<2> scale_src1_opsel;
+  bits<4> src0_modifiers;
+  bits<4> src1_modifiers;
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VigneshwarJ wrote:

I thought so too, but this matches the current src_modifiers field and uses an existing bit mask 4 bit value (OpselHI, OpselLo, Abs and Neg) in TableGen. There is also already a logic in place for asm printing using this bit mask. Also, in previous revision, it was a 2-bit field, which was reading the lower 2 bits hence not generating the right encoding for opsel bits.  Though this MFMA instruction doesn't use neg and abs, I thought it would be cleaner to match the existing implementation. 

https://github.com/llvm/llvm-project/pull/140183