[llvm] [X86] SimplifyDemandedVectorEltsForTargetNode - add X86ISD::MOVDDUP handling (PR #140237)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/140237

Reduce YMM MOVDDUP node to XMM if the upper elements are not demanded

Noticed while working on #140234

>From 627f1d6d65292c5568efaf8b33a5644a9888aabb Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 16 May 2025 11:53:00 +0100
Subject: [PATCH] [X86] SimplifyDemandedVectorEltsForTargetNode - add
 X86ISD::MOVDDUP handling

Reduce YMM MOVDDUP node to XMM if the upper elements are not demanded

Noticed while working on #140234
---
 llvm/lib/Target/X86/X86ISelLowering.cpp        | 2 ++
 llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9be3b39ce16fa..bde4f70b2147f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -44013,6 +44013,8 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
     case X86ISD::VZEXT_MOVL:
       // Variable blend.
     case X86ISD::BLENDV:
+      // Target unary shuffles:
+    case X86ISD::MOVDDUP:
       // Target unary shuffles by immediate:
     case X86ISD::PSHUFD:
     case X86ISD::PSHUFLW:
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
index cf546dc2671f2..d848a8b879215 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
@@ -861,8 +861,7 @@ define <4 x double> @shuffle_v4f64_2345_0567_select(<4 x double> %vec1, <4 x dou
 define <4 x double> @shuffle_v4f64_1436_split_load(ptr %px, ptr %py) {
 ; AVX1-LABEL: shuffle_v4f64_1436_split_load:
 ; AVX1:       # %bb.0:
-; AVX1-NEXT:    vmovapd (%rsi), %xmm0
-; AVX1-NEXT:    vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm0 = mem[0,0]
 ; AVX1-NEXT:    vmovupd (%rdi), %ymm1
 ; AVX1-NEXT:    vinsertf128 $1, 16(%rsi), %ymm0, %ymm0
 ; AVX1-NEXT:    vshufpd {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[2]