[llvm] [WIP][CodeGen] Modifying MBB's liveins representation as into regUnits (PR #129847)

[Jay Foad via llvm-commits]

================
@@ -597,54 +596,67 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
   printName(OS, 0);
 }
 
-void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
-  LiveInVector::iterator I = find_if(
-      LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
-  if (I == LiveIns.end())
-    return;
+void MachineBasicBlock::addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask) {
+  assert(PhysReg.isPhysical() && "live-in should be a physical register");
+  const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
+  for (MCRegUnitMaskIterator U(PhysReg, TRI); U.isValid(); ++U) {
+    LaneBitmask Mask = (*U).second;
+    MCRegUnit Unit = (*U).first;
+    if ((Mask & LaneMask).any())
+      for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+           ++RootReg)
+        LiveIns.insert(*RootReg);
+  }
+}
 
-  I->LaneMask &= ~LaneMask;
-  if (I->LaneMask.none())
-    LiveIns.erase(I);
+void MachineBasicBlock::removeLiveIn(MCRegister Reg, LaneBitmask LaneMask) {
+  assert(Reg.isPhysical() && "live-in should be a physical register");
+  const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
+  for (MCRegUnitMaskIterator U(Reg, TRI); U.isValid(); ++U) {
+    LaneBitmask Mask = (*U).second;
+    MCRegUnit Unit = (*U).first;
+    if ((Mask & LaneMask).any())
+      for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+           ++RootReg)
+        LiveIns.erase(*RootReg);
+  }
 }
 
 MachineBasicBlock::livein_iterator
 MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
-  // Get non-const version of iterator.
-  LiveInVector::iterator LI = LiveIns.begin() + (I - LiveIns.begin());
-  return LiveIns.erase(LI);
+  if (I == LiveIns.end())
+    return I;
+
+  DenseSet<MCRegister>::iterator start = LiveIns.begin();
+  while (start != I)
+    start++;
+  MachineBasicBlock::livein_iterator next = start;
+  LiveIns.erase(start);
+  return next++;
 }
 
 bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
-  livein_iterator I = find_if(
-      LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
-  return I != livein_end() && (I->LaneMask & LaneMask).any();
-}
-
-void MachineBasicBlock::sortUniqueLiveIns() {
-  llvm::sort(LiveIns,
-             [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
-               return LI0.PhysReg < LI1.PhysReg;
-             });
-  // Liveins are sorted by physreg now we can merge their lanemasks.
-  LiveInVector::const_iterator I = LiveIns.begin();
-  LiveInVector::const_iterator J;
-  LiveInVector::iterator Out = LiveIns.begin();
-  for (; I != LiveIns.end(); ++Out, I = J) {
-    MCRegister PhysReg = I->PhysReg;
-    LaneBitmask LaneMask = I->LaneMask;
-    for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
-      LaneMask |= J->LaneMask;
-    Out->PhysReg = PhysReg;
-    Out->LaneMask = LaneMask;
+  if(!Reg.isPhysical())
+    return false;
+
+  const TargetRegisterInfo *TRI = getParent()->getSubtarget().getRegisterInfo();
+  for (MCRegUnitMaskIterator U(Reg, TRI); U.isValid(); ++U) {
+    LaneBitmask Mask = (*U).second;
+    MCRegUnit Unit = (*U).first;
+    if ((Mask & LaneMask).any()) {
+      for (MCRegUnitRootIterator RootReg(Unit, TRI); RootReg.isValid();
+           ++RootReg)
+        if (LiveIns.count(*RootReg))
+          return true;
+    }
   }
-  LiveIns.erase(Out, LiveIns.end());
+  return false;
 }
 
 Register
 MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
   assert(getParent() && "MBB must be inserted in function");
-  assert(PhysReg.isPhysical() && "Expected physreg");
+  assert(PhysReg && "Expected physreg");
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jayfoad wrote:

Why did you change this?

https://github.com/llvm/llvm-project/pull/129847