[llvm] [RISCV] Add SEXT_INREG patterns for Xqcibm ext instruction (PR #140192)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Thu May 15 22:20:47 PDT 2025
https://github.com/svs-quic edited https://github.com/llvm/llvm-project/pull/140192
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